Integrated photonics including germanium

Patent metadata

Field	Value
Publication number	US-10830952-B2
Application number	US-201916396128-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	Jan 5, 2015
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

First claim

What is claimed is:

1. A method of fabricating a photodetector structure comprising:
forming dielectric material over a silicon waveguide;
etching a trench in the dielectric material extending to the silicon waveguide;
epitaxially growing germanium within the trench;
annealing germanium formed by the epitaxially growing;
repeating the epitaxially growing and the annealing;
depositing metal within a second trench, the second trench having a bottom defined by the silicon waveguide and a sidewall defined by the dielectric material;
performing silicide formation annealing so that the metal reacts with the silicon to form a silicide formation at a bottom of the trench; and
performing transformation stage annealing so that the silicide formation is transformed into a low resistivity phase.

2. The method of claim 1 , wherein the depositing metal results in unreacted metal being formed on a sidewall of the second trench, and wherein the method includes forming a capping layer over the metal with the metal in an unreacted state prior to the performing silicide formation annealing.

3. The method of claim 1 , wherein the depositing metal results in unreacted metal being formed on a sidewall of the second trench, wherein the method includes forming a capping layer over the metal with the metal in an unreacted state prior to the performing silicide formation annealing, and wherein the method includes removing the capping layer and the unreacted metal prior to the performing transformation stage annealing.

4. The method of claim 1 , wherein the transformation stage annealing is performed at a higher annealing temperature than the silicide formation annealing.

5. The method of claim 1 , wherein the metal is selected from the group consisting of nickel and nickel platinum.

6. The method of claim 1 , wherein the depositing metal is followed by a second metal deposition overfilling the second trench so that the second metal has a thickness at a top of the second trench that is more than three times a thickness if the silicide formation at the bottom of the second trench.

7. The method of claim 1 , wherein the method of depositing a second metal includes forming copper within the second trench subsequent to formation of the silicide formation (first metal).

8. A photonic structure comprising:
dielectric material formed over a silicon waveguide;
a trench formed in the dielectric material extending to the silicon waveguide;
a germanium formation formed in the trench, the germanium formation adapted to receive light transmitted by the silicon waveguide; and
a top doping region formed in an area of the germanium formation so that the top doping region is spaced from the trench by a first spacing distance equal to or greater than a threshold distance, and a top contact formed on the top doping region, the top contact having a perimeter spaced from a perimeter of the top doping region by a second spacing distance, the second spacing distance being less than the first spacing distance.

9. The photonic structure of claim 8 , wherein a bottom of the trench is defined by a top surface of the silicon waveguide.

10. The photonic structure of claim 8 , wherein a sidewall of the trench at a bottom elevation of the sidewall is delimited by the dielectric material.

11. The photonic structure of claim 8 , having a top contact formed on the top doping region, wherein the top contact is formed of a semiconductor compatible reflective metallization material.

12. The photonic structure of claim 8 , having a top contact formed on the top doping region, wherein the top doping region throughout an area on which the top contact is formed defines a planar surface.

13. The photonic structure of claim 8 , having a top contact formed on the top doping region, wherein the top doping region throughout an area on which the top contact is formed defines a planar surface, wherein the top contact formed on the doping region is formed in an area of the doping region so that an entire perimeter of the contact is spaced from a perimeter of the doping region by a spacing distance that is equal to or greater than a threshold distance wherein the top contact is formed of a semiconductor compatible reflective metallization material.

14. A method comprising:
forming a photodetector having a bottom and top contact;
forming a dielectric layer defining a trench, the trench having an elevation above an elevation of the top contact; and
forming an aluminum metallization layer within the trench, the aluminum metallization layer being in electrical communication with the top contact.

15. The method of claim 14 , wherein the method includes subjecting the aluminum metallization layer to processing so that the aluminum metallization layer defines a termination layer.

16. The method of claim 14 , wherein the forming a dielectric layer defining the trench is performed so that a bottom of the trench has an elevation above a top elevation of the top contact, wherein the method includes using a damascene process to form the aluminum metallization layer, and wherein the method is performed so that the aluminum metallization layer defines an aluminum termination over a copper conductive material formation.

17. The method of claim 14 , wherein the method includes forming a waveguide so that the waveguide occupies elevations in common with elevations occupied by the aluminum metallization layer.

18. The method of claim 14 , wherein the forming the aluminum metallization layer includes depositing aluminum using a process selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD) and evaporation, wherein the method includes performing a low temperature anneal to densify, reflow, or recrystallize the aluminum metallization layer, wherein the forming the aluminum metallization layer includes performing a moderate temperature aluminum metallization compatible with existing (Cu) metallization formations, and wherein the method includes subjecting the aluminum metallization layer to processing to define a contact pad.

19. The method of claim 14 , wherein the method includes planarizing the aluminum metallization layer so that the aluminum metallization layer defines a flat wiring assembly.

20. The method of claim 14 , wherein the method includes performing a dual-patterning and single fill/planarization process where the aluminum metallization layer simultaneously fills the trench and a via below the trench, and wherein the method includes planarizing the aluminum metallization layer.

Assignees

• Univ New York State Res Found

Inventors

• Coolbaugh Douglas
• Adam Thomas
• Leake Gerald L

Classifications

• H10P14/3441

  Conductivity type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title