Radar unit, integrated circuit and methods for detecting and mitigating mutual interference

US10830867B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10830867-B2
Application numberUS-201816012225-A
CountryUS
Kind codeB2
Filing dateJun 19, 2018
Priority dateAug 18, 2017
Publication dateNov 10, 2020
Grant dateNov 10, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A radar unit ( 400 ) for detecting an existence of interference is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit configured support a normal data acquisition mode of operation that comprises transmitting a radar signal waveform and receiving an echo signal thereof; a mixed analog and baseband circuit operably coupled to the mmW Tx/Rx circuit; and a signal processor circuit ( 452 ) operably coupled to the mixed analog and baseband circuit. An interference detection unit ( 448 ) is operably coupled to the mmW Tx/Rx circuit. The radar unit is configured to operate a time-discontinuous mode of operation that includes a first time portion used as an interference monitoring period and a second time portion used by the radar unit in the normal data acquisition mode of operation, whereby the mixed analog and baseband circuit, signal processor circuit ( 452 ) and interference detection unit ( 448 ) are configured to detect interference signals during the monitoring period.

First claim

Opening claim text (preview).

The invention claimed is: 1. A radar unit for detecting an existence of interference, wherein the radar unit comprises: a millimetre wave transceiver circuit configured to support a normal data acquisition mode of operation that comprises transmitting a radar signal waveform and receiving an echo signal thereof; a mixed analog and baseband circuit operably coupled to the millimetre wave transceiver circuit; and a signal processor circuit operably coupled to the mixed analog and baseband circuit; the radar unit characterized by: an interference detection unit operably coupled to the millimetre wave transceiver circuit; and wherein the radar unit is configured to operate a time-discontinuous mode of operation that includes a first time portion used as an interference monitoring period and a second time portion used by the radar unit in the normal data acquisition mode of operation, whereby the mixed analog and baseband circuit, signal processor circuit and interference detection unit are configured to detect interference signals during the monitoring period; wherein the interference detection unit is configured to identify a direction and level of interference of at least one detected interference signal during the monitoring period and output an interference detected signal; and wherein the signal processor circuit is configured to analyse the interference detected signal and quantify a response to the detection; wherein the radar unit further comprises an architecture reconfiguration control unit coupled to the signal processor circuit and the mixed analog and baseband circuit that comprises at least an amplifier, a filter and an analog-to-digital convertor, wherein the architecture reconfiguration control unit is configured in response to the interference detected signal to adjust at least one of: a gain and/or filter bandwidth of the mixed analog and baseband circuit to avoid saturation of the analog-to-digital convertor. 2. The radar unit of claim 1 wherein the interference detection unit is configured to detect an existence of interference before the radar unit commences the normal radar target acquisition mode of operation. 3. The radar unit of claim 2 wherein the radar unit only powers on receiver circuits to scan at least a portion of supported radar frequency sub-bands during the first time portion. 4. The radar unit of claim 2 further comprising a waveform generator coupled to the signal processor circuit and configured to generate a frequency chirp sequence waveform during the second time portion of a chirp interval, wherein the time-discontinuous mode of operation is performed in each of a plurality of chirp intervals with a start frequency and an end frequency of the chirps in one chirp sequence being the same, and wherein at least one of the following exists: where a start frequency and an end frequency of the chirps is different between each chirp sequence; or where a start frequency and an end frequency of the chirps is the same across a plurality of chirp sequences. 5. The radar unit of claim 2 further comprising a waveform generator coupled to the signal processor circuit and configured to generate a frequency chirp sequence waveform during the second time portion of a chirp interval, wherein the time-discontinuous mode of operation is performed in each of a plurality of chirp intervals with a start frequency and an end frequency of the chirps in one chirp sequence being the same, and wherein at least one of the following exists: where a start frequency and an end frequency of the chirps is different between each chirp sequence; or where a start frequency and an end frequency of the chirps is the same across a plurality of chirp sequences. 6. The radar unit of claim 2 wherein the signal processor circuit re-configures at least one receiver path of multiple receiver paths in the mixed analog and baseband circuit and the millimetre wave transceiver circuit as at least one mutual interference detector receiver. 7. The radar unit of claim 1 wherein the radar unit only powers on receiver circuits to scan at least a portion of supported radar frequency sub-bands during the first time portion. 8. The radar unit of claim 1 further comprising a waveform generator coupled to the signal processor circuit and configured to generate a frequency chirp sequence waveform during the second time portion of a chirp interval, wherein the time-discontinuous mode of operation is performed in each of a plurality of chirp intervals with a start frequency and an end frequency of the chirps in one chirp sequence being the same, and wherein at least one of the following exists: where a start frequency and an end frequency of the chirps is different between each chirp sequence; or where a start frequency and an end frequency of the chirps is the same across a plurality of chirp sequences. 9. The radar unit of claim 8 wherein the waveform generator is configured to generate a set of fixed frequencies that correspond to a center frequency of each sub-band to be monitored in the first time portion. 10. The radar unit of claim 1 wherein the millimetre wave transceiver circuit comprises a transmitter phase array and in response to the indication of the arrival direction of the detected interference signal, the signal processor circuit is configured to adjust at least one parameter of the transmitter phase array to reduce the level of interference. 11. The radar unit of claim 10 wherein the signal processor circuit is configured to steer an antenna beam of the transmitter phase array to reduce the level of interference. 12. The radar unit of claim 10 wherein the signal processor circuit is configured to steer an antenna beam to perform at least one of: spatial filtering to reduce the level of interference; create one or more beam nulls focused towards the direction of the detected interference signal to reduce the level of interference. 13. The radar unit of claim 1 wherein the architecture reconfiguration control unit is coupled to a waveform generator and configured in response to a detected interference signal to adjust at least one of: a chirp bandwidth, a chirp duration, a starting chirp frequency, an ending chirp frequency. 14. The radar unit of claim 1 wherein the signal processor circuit re-configures at least one receiver path of multiple receiver paths in the mixed analog and baseband circuit and the millimetre wave transceiver circuit as at least one mutual interference detector receiver. 15. The radar unit of claim 1 further comprising an auxiliary detection path incorporating at least one auxiliary receiver coupled to the interference detection unit and comprising one or more programmable bandpass filter(s), one or more programmable gain amplifiers, PGAs, and an analog to digital converter, and configured to detect the interference signal. 16. The radar unit of claim 15 wherein the auxiliary detection path includes a number of wideband receivers configured to cover the complete radar operational bandwidth to detect both frequency and direction of interference signals.

Assignees

Inventors

Classifications

  • G01S7/023Primary

    Interference mitigation, e.g. reducing or avoiding non-intentional interference with other HF-transmitters, base station transmitters for mobile communication or other radar systems, e.g. using electro-magnetic interference [EMI] reduction techniques (auxiliary means for detecting or identifying radar signals or the like G01S7/021; means for anti-jamming G01S7/36) · CPC title

  • Avoidance by space multiplex · CPC title

  • Avoidance by frequency multiplex · CPC title

  • Means for monitoring or calibrating · CPC title

  • Active array antenna · CPC title

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Frequently asked questions

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What does patent US10830867B2 cover?
A radar unit ( 400 ) for detecting an existence of interference is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit configured support a normal data acquisition mode of operation that comprises transmitting a radar signal waveform and receiving an echo signal thereof; a mixed analog and baseband circuit operably coupled to the mmW Tx/Rx circuit; and a signal processo…
Who is the assignee on this patent?
Nxp Bv
What technology area does this patent fall under?
Primary CPC classification G01S7/023. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 10 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).