Integrating ramp circuit with reduced ramp settling time

Patent metadata

Field	Value
Publication number	US-10826470-B2
Application number	US-201916352673-A
Country	US
Kind code	B2
Filing date	Mar 13, 2019
Priority date	Mar 13, 2019
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

First claim

What is claimed is:

1. A ramp generator, comprising:
an integrator amplifier having first and second inputs and an output to generate a ramp signal, wherein the integrator amplifier comprises:
a first stage having first and second inputs and first and second outputs, wherein the first and second inputs of the first stage are coupled to the first and second inputs of the integrator amplifier;
a second stage, comprising:
first and second transistors coupled between a power supply rail and ground, wherein a node between the first and second transistors is coupled to the output of the integrator amplifier, wherein a control terminal of the first transistor is coupled to the first output of the first stage, and wherein a control terminal of the second transistor is coupled to the second output of the first stage, wherein a first current flows from the output of the integrator amplifier through the integrator amplifier to ground during a ramp event in the ramp signal generated from the output of the integrator amplifier; and
trimming circuitry coupled between the power supply rail and the output of the integrator amplifier, wherein the trimming circuitry is coupled to provide a second current to the output of the integrator amplifier in response to trimming inputs, wherein the second current substantially matches the first current.

2. The ramp generator of claim 1 , wherein the trimming circuitry is further coupled to the first output of the first stage, wherein the trimming circuitry comprises a plurality of transistors coupled between the power supply rail and the output of the integrator amplifier, wherein the plurality of transistors are coupled to provide the second current to the output of the integrator amplifier in response to the trimming inputs.

3. The ramp generator of claim 1 , wherein the integrator amplifier comprises a first op amp including the first stage and the second stage, wherein the first stage of the first op amp comprises a second op amp having the first and second inputs and the first and second outputs.

4. The ramp generator of claim 1 , further comprising:
a capacitor coupled between the first input and the output of the integrator amplifier; and
a current source coupled to the first input of the integrator amplifier.

5. The ramp generator of claim 1 , further comprising an enable switch coupled between the between the first input and the output of the integrator amplifier, wherein the enable switch is configured to enable and disable the integrator amplifier.

6. The ramp generator of claim 1 , further comprising:
a reference voltage capacitance coupled to provide a reference input voltage to the second input of the integrator amplifier; and
a sampling switch coupled between a reference voltage and the second capacitor, wherein the sampling switch is configured to sample the reference voltage onto the reference voltage capacitance.

7. An imaging system, comprising:
an array of pixels to receive image light and generate an image charge voltage signal in response; and
readout circuitry coupled to the receive the image charge voltage signal from the array of pixels and provide a digital representation of the image charge voltage signal in response, the readout circuitry including a comparator to receive the image charge, compare the image charge voltage signal to a ramp signal from a ramp generator, and provide the digital representation of the image charge voltage signal in response, wherein the ramp generator comprises:
an integrator amplifier having first and second inputs and an output to generate the ramp signal, wherein the integrator amplifier comprises:
a first stage having first and second inputs and first and second outputs, wherein the first and second inputs of the first stage are coupled to the first and second inputs of the integrator amplifier;
a second stage, comprising:
first and second transistors coupled between a power supply rail and ground, wherein a node between the first and second transistors is coupled to the output of the integrator amplifier, wherein a control terminal of the first transistor is coupled to the first output of the first stage, and wherein a control terminal of the second transistor is coupled to the second output of the first stage, wherein a first current flows from the output of the integrator amplifier through the integrator amplifier to ground during a ramp event in the ramp signal generated from the output of the integrator amplifier; and
trimming circuitry coupled between the power supply rail and the output of the integrator amplifier, wherein the trimming circuitry is coupled to provide a second current to the output of the integrator amplifier in response to trimming inputs, wherein the second current substantially matches the first current.

8. The imaging system of claim 7 , wherein the trimming circuitry is further coupled to the first output of the first stage, wherein the trimming circuitry comprises a plurality of transistors coupled between the power supply rail and the output of the integrator amplifier, wherein the plurality of transistors are coupled to provide the second current to the output of the integrator amplifier in response to the trimming inputs.

9. The imaging system of claim 7 , wherein the integrator amplifier comprises a first op amp including the first stage and the second stage, wherein the first stage of the first op amp comprises a second op amp having the first and second inputs and the first and second outputs.

10. The imaging system of claim 7 , wherein the integrator amplifier comprises:
a capacitor coupled between the first input and the output of the integrator amplifier; and
a current source coupled to the first input of the integrator amplifier.

11. The imaging system of claim 7 , wherein the integrator amplifier comprises an enable switch coupled between the between the first input and the output of the integrator amplifier, wherein the enable switch is configured to enable and disable the integrator amplifier.

12. The imaging system of claim 7 , wherein the ramp generator further comprises:
a reference voltage capacitance coupled to provide a reference input voltage to the second input of the integrator amplifier; and
a sampling switch coupled between a reference voltage and the second capacitor, wherein the sampling switch is configured to sample the reference voltage onto the reference voltage capacitance.

13. A method for reducing a delay of a ramp event in a ramp signal of a ramp generator, comprising:
generating the ramp signal at an output of an op amp having first and second inputs, wherein the op amp is included in the ramp generator;
coupling an integrator capacitor between the first input and the output of the op amp;
coupling a current source to the first input of the op amp;
coupling a reference voltage capacitance to the second input of the op amp;
sampling a reference voltage onto the reference voltage capacitance with a sampling switch coupled between the reference voltage and the reference voltage capacitance; and
reducing the reference voltage sampled onto the reference voltage capacitance during the ramp event in the ramp signal with a tuning circuit coupled to the second input of the op amp to reduce the delay of the ramp event in the ramp signal.

14. The method of claim 13 , further comprising enabling and disabling the ramp generator with an enable switch coupled between the between the first input and the output of the op amp.

15. The method of claim 13 , wherein the tuning circuit comprises:
a tuning capacitance coupled to the second input of the op amp; a

Assignees

• Omnivision Tech Inc

Inventors

• Zuo Liang
• Wang Rui
• Ebihara Hiroaki
• Jiang Nijun

Classifications

• H04N25/709

  Circuitry for control of the power supply · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title