Signal processing circuit, solid-state imaging device, and camera system

Patent metadata

Field	Value
Publication number	US-9307173-B2
Application number	US-201113064911-A
Country	US
Kind code	B2
Filing date	Apr 26, 2011
Priority date	May 13, 2010
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

First claim

What is claimed is:

1. A signal processing circuit comprising:
a reference signal generating circuit configured to generate a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and
a signal processing unit including a plurality of processing sections respectively configured to process the reference signal and a potential of a supplied analog signal,
wherein the reference signal generating circuit is configured to adjust an offset of the reference signal by adjusting the current from the time of starting the generation of a ramp portion of the reference signal or to adjust the level of the reference signal at least at the time of starting the generation of the rams portion of the reference signal, and
wherein the reference signal generating circuit adjusts the offset of the reference signal by a fixed amount for a predetermined period of time, wherein the predetermined period of time is substantially coextensive with the ramp portion of the reference signal.

2. The signal processing circuit according to claim 1 , wherein the reference signal generating circuit includes a synchronization circuit configured to make a synchronization to absorb a difference between a start time of generating the ramp portion of the reference signal and a current application time.

3. The signal processing circuit according to claim 1 , wherein the reference signal generating circuit includes a circuit configured to automatically adjust the offset of the reference signal, when the slope of the reference signal is variable and the slope of the reference signal varies.

4. The signal processing circuit according to claim 1 , wherein the reference signal generating circuit includes:
a reference-signal generating current source that is connected to an output node of the reference signal; and
an output load portion that is connected to the output node and is configured to allow the reference signal of a level corresponding to a reference-signal current from the reference-signal generating current source to appear at the output node,
wherein the output load portion is configured to set its load value to a first load value before starting the generation of the reference signal and to set its load value to a second load value different from the first load value at the time of starting the generation of the ramp portion of the reference signal.

5. The signal processing circuit according to claim 4 , wherein the reference signal generating circuit is configured to set the load value of the output load portion to the second load value for the predetermined period of time from the time of starting the generation of the ramp portion of the reference signal and to set the load value of the output load portion to the first load value after the predetermined period of time passes.

6. The signal processing circuit according to claim 4 , wherein the output load section of the reference signal generating circuit includes a plurality of adjusting loads, the output load section configured to adjust the number of the plurality of adjusting loads to give an offset to the reference signal.

7. The signal processing circuit according to claim 1 , wherein the reference signal generating circuit is configured to allow a settling current other than the current for generation of the reference signal to flow for the predetermined period of time from the time of starting the generation of the ramp portion of the reference signal.

8. The signal processing circuit according to claim 7 , wherein the reference signal generating circuit includes a plurality of current sources respectively configured to allow a current to flow at the time of starting the generation of the ramp portion of the reference signal, the reference signal generating circuit configured to adjust the number of the plurality of current sources to give the offset to the reference signal.

9. The signal processing circuit according to claim 7 , wherein the reference signal generating circuit includes:
a reference-signal generating current source configured to generate the reference signal; and
a settling-current current source configured to allow the settling current to flow.

10. The signal processing circuit according to claim 9 , wherein the reference signal generating circuit is configured to switch a back-bias voltage of a reference-voltage generating current source transistor.

11. A solid-state imaging device comprising:
a pixel unit in which a plurality of pixels performing a photoelectric conversion are arranged in a matrix shape; and
a pixel signal reading unit including a column signal processing circuit configured to read pixel signals from the pixel unit to signal lines in terms of a plurality of pixels and to perform an analog-digital (AD) conversion on the read pixel signals,
wherein the column signal processing circuit of the pixel signal reading unit includes
a reference signal generating circuit configured to generate a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current,
a plurality of comparators respectively configured to compare the reference signal with a potential of an analog signal read from the corresponding column, and
a plurality of counter latches respectively disposed to correspond to the plurality of comparators, and configured to count a comparison time of the corresponding comparator, and to stop the counting and latch the counted value when the output of the corresponding comparator is inverted,
wherein the reference signal generating circuit is configured to adjust an offset of the reference signal by adjusting the current from the time of starting the generation of the a ramp portion of reference signal or to adjust the level of the reference signal at least at the time of starting the generation of the ramp portion of the reference signal, and
wherein the reference signal generating circuit adjusts the offset of the reference signal by a fixed amount for a predetermined period of time, wherein the predetermined period of time is substantially coextensive with the ramp portion of the reference signal.

12. The signal solid-state imaging device according to claim 11 , wherein the reference signal generating circuit includes a synchronization circuit configured to make a synchronization to absorb a difference between a start time of generating the ramp portion of the reference signal and a current application time.

13. The solid-state imaging device according to claim 11 , wherein the reference signal generating circuit includes:
a reference-signal generating current source that is connected to an output node of the reference signal; and
an output load portion that is connected to the output node and is configured to allow the reference signal of a level corresponding to a reference-signal current from the reference-signal generating current source to appear at the output node,
wherein the output load portion is configured to set its load value to a first load value before starting the generation of the ramp portion of the reference signal and to set its load value to a second load value different from the first load value at the time of starting the generation of the ramp portion of the reference signal.

14. The solid-state imaging device according to claim 11 , wherein the reference signal generating circuit includes a circuit configured to automatically adjust the offset of the reference signal, when the slope of the reference signal is variable and the slope of the reference signal varies.

15. The solid-state imaging device according to cl

Assignees

• Takamiya Kenichi
• Gendai Yuji
• Hisamatsu Yasuaki
• Nagata Tadafumi
• Sony Corp

Inventors

• Takamiya Kenichi
• Gendai Yuji
• Hisamatsu Yasuaki
• Nagata Tadafumi

Classifications

• H03M1/0612 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title