Heterostructure and method of fabrication

Patent metadata

Field	Value
Publication number	US-10826459-B2
Application number	US-201615735477-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Jun 12, 2015
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

First claim

The invention claimed is:

1. A method of fabricating a heterostructure comprising a layer of piezoelectric material on a support substrate, the method comprising:
forming a polycrystalline silicon trap-rich layer on a surface of a silicon substrate;
providing a piezoelectric material to be molecularly bonded to the silicon substrate;
forming an oxide layer on a surface of at least one of the trap-rich layer and the piezoelectric material;
molecularly bonding the piezoelectric material and the silicon substrate such that the oxide layer is located at an interface between the piezoelectric material and the polycrystalline silicon trap-rich layer formed on the silicon substrate, thereby forming a piezoelectric structure; and
thinning the piezoelectric structure after the molecular bonding of the piezoelectric material and the silicon substrate.

2. The method of claim 1 wherein thinning the piezoelectric structure comprises implanting atomic or ionic species into the piezoelectric material prior to molecularly bonding the piezoelectric material and the silicon substrate, to form a zone of weakness in the piezoelectric material, and fracturing the piezoelectric material along the zone of weakness after molecularly bonding the piezoelectric material and the silicon substrate so as to exfoliate a layer of the piezoelectric material.

3. The method of claim 1 , wherein the thinning of the piezoelectric structure is performed by at least one technique chosen from among the group consisting of grinding, polishing, and etching.

4. The method of claim 1 , further comprising selecting the piezoelectric material to comprise a material selected from the group consisting of LTO, LNO, AlN, and ZnO.

5. The method of claim 1 , wherein the piezoelectric material exhibits a first coefficient of thermal expansion, and the silicon substrate exhibits a different second coefficient of thermal expansion.

6. The method of claim 5 , wherein at least one of the first coefficient of thermal expansion and the second coefficient of thermal expansion exhibits anisotropy.

7. The method of claim 1 , wherein the polycrystalline silicon trap-rich layer provides the silicon substrate with an electrical resistivity higher than 1 kOhm/cm.

8. The method of claim 7 , wherein the polycrystalline silicon trap-rich layer provides the silicon substrate with an electrical resistivity higher than 5 kOhm/cm.

9. The method of claim 1 , wherein the polycrystalline silicon trap-rich layer has a thickness below 10 μm.

10. The method of claim 1 , further comprising forming at least one recess in the piezoelectric material prior to molecularly bonding the piezoelectric material and the silicon substrate.

11. The method of claim 10 , wherein the thinning of the piezoelectric structure exposes the at least one recess at a surface of the piezoelectric structure on the side thereof opposite the interface.

12. The method of claim 10 , wherein forming the at least one recess in the piezoelectric material comprises forming at least one trench extending entirely across the piezoelectric material.

13. The method of claim 10 , wherein forming the at least one recess in the piezoelectric material comprises forming parts of the piezoelectric material separated by the at least one recess to have a lateral dimension smaller than a predetermined critical length above which breakage due to a thermal treatment at a predefined temperature would occur.

Assignees

• Soitec Silicon On Insulator

Inventors

• Castex Arnaud
• Delprat Daniel
• Aspar Bernard
• Radu Ionut

Classifications

• H03H3/10

  for obtaining desired frequency or temperature coefficient · CPC title

• H03H9/02834 Primary

  of temperature influence (cut angles H03H9/02543) · CPC title

• H03H3/04

  for obtaining desired frequency or temperature coefficient · CPC title

• H10N30/704 Primary

  based on piezoelectric or electrostrictive films or coatings · CPC title

• H03H9/02574

  of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate · CPC title