MIM capacitor with top electrode having footing profile and method forming same

Patent metadata

Field	Value
Publication number	US-10825892-B2
Application number	US-202016741058-A
Country	US
Kind code	B2
Filing date	Jan 13, 2020
Priority date	Mar 24, 2016
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a bottom electrode;
a capacitor insulator over the bottom electrode;
a top electrode over the capacitor insulator, wherein the top electrode comprises a first sidewall and a second sidewall opposing to each other, wherein the first sidewall and the second sidewall extend to the capacitor insulator, and the top electrode has a footing profile, with lower widths of the top electrode being increasingly greater than respective upper widths of the top electrode, and wherein the lower widths and the upper widths are measured from the first sidewall to the second sidewall;
a first dielectric layer over and contacting the top electrode, wherein the first dielectric layer has vertical sidewalls;
a second dielectric layer covering the top electrode and the first dielectric layer;
a polymer layer; and
a redistribution line comprising:
a line portion over the polymer layer; and
a via portion extending into the polymer layer, wherein the via portion is electrically connected to one of the top electrode and the bottom electrode.

2. The integrated circuit structure of claim 1 , wherein the capacitor insulator laterally extends beyond the first sidewall and the second sidewall of the top electrode.

3. The integrated circuit structure of claim 2 further comprising a contact plug, wherein the contact plug penetrates through the capacitor insulator to contact the bottom electrode.

4. The integrated circuit structure of claim 1 , wherein the first dielectric layer has a top width and a bottom width equal to the top width, and wherein the bottom width is equal to an additional top width of the top electrode.

5. The integrated circuit structure of claim 1 , wherein the bottom electrode and the second dielectric layer are in the polymer layer.

6. The integrated circuit structure of claim 1 , wherein the capacitor insulator comprises third sidewalls flush with corresponding fourth sidewalls of the bottom electrode.

7. The integrated circuit structure of claim 1 , wherein the capacitor insulator comprises zirconium oxide.

8. The integrated circuit structure of claim 1 , wherein the top electrode comprises TiN.

9. The integrated circuit structure of claim 1 , wherein the first sidewall and the second sidewall of the top electrode are flushed with respective ones of the vertical sidewalls of the first dielectric layer.

10. The integrated circuit structure of claim 1 , wherein the polymer layer comprises polyimide or polybenzoxazole.

11. An integrated circuit structure comprising:
a capacitor comprising:
a bottom electrode;
a capacitor insulator over the bottom electrode; and
a top electrode over the capacitor insulator, wherein the top electrode has a top width and a bottom width greater than the top width, with both of the top width and the bottom width being measured from a same first sidewall to a same second sidewall of the top electrode, and wherein the capacitor insulator extends laterally beyond the top electrode;

a first dielectric layer comprising:
a first portion overlapping the top electrode; and
a second portion extending on, and contacting, the same first sidewall and the same second sidewall of the top electrode; and

a second dielectric layer over and contacting the top electrode, wherein the second dielectric layer comprises an additional sidewall flush with a top portion of the same first sidewall, and wherein the additional sidewall is vertical.

12. The integrated circuit structure of claim 11 , wherein the same first sidewall is straight and slanted.

13. The integrated circuit structure of claim 11 , wherein the second dielectric layer has an additional bottom width equal to the top width of the top electrode.

14. The integrated circuit structure of claim 11 , wherein the same first sidewall has a tilt angle in a range between about 80 degrees and about 85 degrees.

15. The integrated circuit structure of claim 11 further comprising a contact plug, wherein the contact plug penetrates through the capacitor insulator and the first dielectric layer to contact the bottom electrode.

16. The integrated circuit structure of claim 11 further comprising:
a polymer layer; and
a redistribution line comprising:
a line portion over the polymer layer; and
a via portion extending into the polymer layer, wherein the via portion electrically connects the line portion to the bottom electrode.

17. The integrated circuit structure of claim 16 , wherein the capacitor is in the polymer layer.

18. An integrated circuit structure comprising:
a bottom electrode comprising a first sidewall;
a capacitor insulator over the bottom electrode, wherein the capacitor insulator comprises a second sidewall flush with the first sidewall;
a top electrode over the capacitor insulator, wherein the top electrode comprises a third sidewall and a fourth sidewall opposing the third sidewall, and wherein the third sidewall and the fourth sidewall are slanted;
a first dielectric layer overlapping the top electrode; and
a second dielectric layer comprising:
a first portion overlapping the first dielectric layer; and
a second portion and a third portion contacting the third sidewall and the fourth sidewall, respectively.

19. The integrated circuit structure of claim 18 , wherein the second dielectric layer further comprises a fourth portion forming a horizontal interface with a top surface of the capacitor insulator.

20. The integrated circuit structure of claim 18 further comprising:
a metal pad;
a passivation layer on the metal pad;
a polymer layer over the passivation layer, wherein the bottom electrode and the top electrode are in the polymer layer; and
a redistribution line comprising:
a line portion over the polymer layer; and
a via portion extending into the polymer layer to contact the metal pad, wherein the via portion is electrically connected to the top electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hung-Hao
• Chang Che-Cheng
• Chen Wen-Tung
• Liu Yu-Cheng
• Tseng Horng-Huei

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• H01L2224/11

  Electricity · mapped topic