Etching process control in forming MIM capacitor

Patent metadata

Field	Value
Publication number	US-10008559-B2
Application number	US-201715420660-A
Country	US
Kind code	B2
Filing date	Jan 31, 2017
Priority date	Mar 24, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

First claim

What is claimed is:

1. A method comprising:
forming a capacitor comprising:
depositing a bottom electrode layer;
depositing a capacitor insulator layer over the bottom electrode layer;
depositing a top electrode layer over the capacitor insulator layer;
depositing a dielectric layer over the top electrode layer; and
etching the dielectric layer using a first process gas until the top electrode layer is exposed, wherein the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate in response to the first process gas, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

2. The method of claim 1 further comprising etching the top electrode layer using a second process gas different from the first process gas.

3. The method of claim 2 , wherein the first process gas comprises CF 4 , with the first process gas being substantially pure CF 4 .

4. The method of claim 2 , wherein the second process gas comprises CHF 3 and chlorine (Cl 2 ).

5. The method of claim 1 further comprising forming a patterned photo resist over the dielectric layer, wherein the dielectric layer is etched using the patterned photo resist as an etching mask.

6. The method of claim 2 , wherein the etching the top electrode layer results in a remaining portion as a top electrode, and the top electrode has a footing profile, with lower portions of the top electrode being increasingly wider than respective upper portions of the top electrode.

7. The method of claim 1 , wherein the etching the dielectric layer comprises applying a bias power lower than about 130 Watts.

8. The method of claim 1 , wherein the depositing the bottom electrode layer comprises depositing titanium nitride (TiN), and the depositing the capacitor insulator layer comprises depositing a zirconium oxide layer.

9. A method comprising:
depositing a bottom electrode layer on a wafer;
depositing a capacitor insulator layer over the bottom electrode layer;
depositing a top electrode layer over the capacitor insulator layer;
depositing a dielectric layer over the top electrode layer; and
etching the dielectric layer using a first process gas, wherein the first process gas comprises CF 4 , and is substantially free from additional carbon-and-fluorine-containing gases; and
etching the top electrode layer using a second process gas to form a top electrode, wherein the second process gas comprises fluorine, and is substantially free from CF 4 , wherein a capacitor insulator layer is exposed after the top electrode layer is etched.

10. The method of claim 9 further comprising forming a patterned photo resist over the dielectric layer, wherein the dielectric layer is etched using the patterned photo resist as an etching mask.

11. The method of claim 9 , wherein the dielectric layer has a first etching rate in response to the first process gas, and the top electrode layer has a second etching rate in response to the first process gas, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

12. The method of claim 9 , wherein the top electrode has a footing profile.

13. The method of claim 9 further comprising:
forming a plurality of sample wafers having top electrode layers and dielectric layers identical to the top electrode layer and the dielectric layer in the wafer, respectively; and
adjusting process gases and etching process conditions for etching the dielectric layer on the plurality of sample wafers to find a process gas and an etching process condition that will result in an etching selectivity to be higher than about 5.0.

14. The method of claim 9 , wherein the etching the dielectric layer is performed by applying a bias power lower than about 130 Watts.

15. The method of claim 9 , wherein the first process gas comprises CF 4 , and is free from CHF 3 , and the second process gas comprises CHF 3 and is substantially free from CF 4 .

16. The method of claim 15 , wherein the first process gas comprises substantially pure CF 4 .

17. A method comprising:
depositing a bottom electrode layer on a wafer;
depositing a capacitor insulator layer over the bottom electrode layer;
depositing a top electrode layer over the capacitor insulator layer;
depositing a dielectric layer over the top electrode layer;
etching the dielectric layer using a first process gas until the top electrode layer is exposed;
etching the top electrode layer using a second process gas to form a top electrode, wherein the top electrode has a footing profile, with lower portions of the top electrode being increasingly wider than respective upper portions of the top electrode;
forming an additional dielectric layer covering the top electrode and a remaining portion of the dielectric layer; and
patterning the additional dielectric layer, the capacitor insulator layer, and the bottom electrode layer to form a capacitor.

18. The method of claim 17 , wherein in a cross-sectional view of the capacitor, the top electrode has a substantially straight and slanted edge with a tilting angle smaller than about 85 degrees.

19. The method of claim 17 , wherein the first process gas comprises substantially pure CF 4 , and the second process gas comprise fluorine, and is substantially free from CF 4 .

20. The method of claim 17 , wherein the dielectric layer has a first etching rate in response to the first process gas, and the top electrode layer has a second etching rate in response to the first process gas, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hung-Hao
• Chang Che-Cheng
• Chen Wen-Tung
• Liu Yu-Cheng
• Tseng Horng-Huei

Classifications

• H10W72/012

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  Electricity · mapped topic

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• H10D1/682

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• H10D1/692 Primary

  Electrodes · CPC title