Resistive random access memory and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9608204-B2
Application number	US-201314021364-A
Country	US
Kind code	B2
Filing date	Sep 9, 2013
Priority date	Sep 9, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a conductive layer;
a resistance configurable structure over the conductive layer, the resistance configurable structure comprising:
a first electrode comprising a first sidewall, a second sidewall, and a bottom surface on the conductive layer, wherein the first sidewall and the second sidewall form an electric field enhancement structure;
a resistance configurable layer over the first electrode; the resistance configurable layer having a first portion and a second portion, wherein the first portion is in direct contact with the conductive layer, and the second portion comprising a dielectric layer between the resistance configurable layer and the conductive layer; and
a second electrode over the resistance configurable layer.

2. The semiconductor in claim 1 , wherein the electric field enhancement structure comprises an angle about or less than 90 degrees.

3. The semiconductor in claim 1 , wherein a ratio of a thickness of the dielectric layer with respect to a height of the first sidewall is in a range of from about 0.2 to about 1.0.

4. The semiconductor in claim 1 , wherein the second electrode comprises an oxygen depriving layer contacting the resistance configurable layer, the oxygen depriving layer configured to deprive oxygen from the resistance configurable layer.

5. The semiconductor in claim 1 , wherein the bottom surface of the first electrode comprises a width about or less than 20 nm.

6. The semiconductor in claim 1 , wherein the resistance configurable layer comprises a thickness about or less than 150 angstrom.

7. The semiconductor in claim 1 , wherein each of the first electrode and the second electrode comprises at least one selected from the group consisting essentially of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu.

8. The semiconductor in claim 1 , wherein the resistance configurable layer comprises at least one selected from the group consisting essentially of high-k dielectric material, a binary metal oxide, a transition metal oxide, and a lanthanide metal oxide.

9. A resistive random access memory (RRAM), comprising:
a first dielectric layer comprising a top surface;
a metal-insulator-metal (MIM) structure positioned on the first dielectric layer, the MIM structure comprising:
a first electrode on the top surface of the first dielectric layer, the first electrode comprising an electric field enhancement structure with a first sidewall perpendicular to the top surface of the dielectric layer and a second sidewall comprising an arc;
a resistance configurable layer over the electric field enhancement structure, being in physical contact with the first sidewall and the second sidewall; and
a second electrode over the resistance configurable layer.

10. The RRAM in claim 9 , one end of the arc connecting to the first sidewall.

11. The RRAM in claim 9 , wherein the first electrode comprises a spacer.

12. The RRAM in claim 9 , further comprising a second dielectric layer on the first electrode, contacting at least a portion of the first sidewall.

13. The RRAM in claim 9 , wherein the second electrode comprises an oxygen depriving layer contacting the resistance configurable layer, the oxygen depriving layer configured to deprive oxygen from the resistance configurable layer.

14. The RRAM in claim 9 , the resistance configurable layer conforming a contour of the electric field enhancement structure.

15. The RRAM in claim 13 , the oxygen depriving layer conforming a contour of the resistance configurable layer.

16. A resistive random access memory (RRAM), comprising:
a conductive structure;
a metal-insulator-metal (MIM) structure positioned on the conductive structure, the MIM structure comprising:
an electrode comprising a planar portion and an electric field enhancement structure, the electric field enhancement structure comprising a first sidewall perpendicular to a top surface of the planar portion and a second sidewall being an arc;
a resistance configurable layer over the electrode and being in physical contact with the first sidewall and the second sidewall.

17. The RRAM in claim 9 , wherein the resistance configurable layer of the MIM structure comprises high-k dielectric, binary metal oxides, transition metal oxides, or lanthanide series metal oxides.

18. The RRAM in claim 9 , further comprising an oxygen depriving layer between the second electrode and the resistance configurable layer, the oxygen depriving layer including Ti, Ta, Hf, or the combination thereof.

19. The RRAM in claim 16 , wherein the resistance configurable layer comprises a bend over a joint connecting the second sidewall and the planar portion of the first electrode.

20. The semiconductor in claim 1 , wherein the dielectric layer comprises silicon dioxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Po-Hao
• Chou Chung-Cheng
• Chu Wen-Ting

Classifications

• H01L45/08

  Electricity · mapped topic

• H01L45/1683 Primary

  Electricity · mapped topic

• H01L45/124

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/1273

  Electricity · mapped topic