Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit

Patent metadata

Field	Value
Publication number	US-10825820-B2
Application number	US-201816174189-A
Country	US
Kind code	B2
Filing date	Oct 29, 2018
Priority date	Jan 19, 2016
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

First claim

The invention claimed is:

1. A microelectronic circuit, comprising:
a substrate,
a transistor,
a memory transistor comprising at least one capacitor, and
source contacts, bulk contacts and drain contacts for the transistor and the memory transistor,
wherein the transistor comprises at least one insulating layer and at least one metal layer,
wherein the memory transistor comprises at least one insulating layer and at least one metal layer,
wherein the insulating layer of the transistor and the insulating layer of the memory transistor are produced in a common step,
wherein the metal layer of the transistor and the metal layer of the memory transistor are produced in a common step,
wherein the metal layer of the memory transistor and the insulating layer of the memory transistor are parts of a MOS capacitor,
wherein a gate contact of the transistor is connected to the metal layer of the transistor, and
wherein a gate contact of the memory transistor is connected to a metal layer of the capacitor of the memory transistor.

2. The microelectronic circuit of claim 1 , manufactured using a method comprising:
providing the substrate,
producing a source contact, a bulk contact and a drain contact each for the transistor and for the memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing the gate contact connected to a metal layer of the capacitor of the memory transistor.

3. A microelectronic circuit, comprising:
a substrate,
a transistor,
a memory transistor comprising at least one capacitor, and
source contacts, bulk contacts and drain contacts for the transistor and the memory transistor,
wherein the transistor comprises at least one insulating layer and at least one metal layer,
wherein the memory transistor comprises at least one insulating layer and at least one metal layer,
wherein the insulating layer of the transistor and the insulating layer of the memory transistor are produced in a common step,
wherein the metal layer of the transistor and the metal layer of the memory transistor are produced in a common step,
wherein a gate contact of the transistor is connected to the metal layer of the transistor, and
wherein a gate contact of the memory transistor is connected to a metal layer of the capacitor of the memory transistor,
wherein the layers of the memory transistor and the layers of the transistor are in a dielectric carrier, and
wherein a further metal layer is on the insulating layer and below a lower metal layer of the memory transistor, and wherein an intermediate conductive path is between the lower metal layer and the further metal layer in the dielectric carrier.

4. The microelectronic circuit of claim 3 ,
manufactured using a method comprising:
providing the substrate,
producing a source contact, a bulk contact and a drain contact each for the transistor and for the memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing the gate contact connected to a metal layer of the capacitor of the memory transistor.

Assignees

• Fraunhofer Ges Forschung

Inventors

• Mueller Johannes
• Polakowski Patrick
• Drescher Maximilian
• Riedel Stefan

Classifications

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D62/378 Primary

  Contact regions to the substrate regions · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title