MOS transistors having low offset values, electronic devices including the same, and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9136264-B2
Application number	US-201414253493-A
Country	US
Kind code	B2
Filing date	Apr 15, 2014
Priority date	Dec 17, 2013
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A MOS transistor includes a gate electrode disposed over an active region without overlapping with an isolation region, the active region including a channel region, the isolation region defining the active region, a source region and a drain region disposed in first and second portions of the active region, respectively, the first and second portions being disposed at first and second sides of the gate electrode, respectively, the first side opposing the second side, a first blocking region disposed in a third portion of the active region between a third side of the gate electrode and the isolation region and between the source and the drain region, and a second blocking region disposed in a fourth portion of the active region between a fourth side of the gate electrode and the isolation region and between the source and the drain region, the fourth side opposing the third side.

First claim

What is claimed is:

1. A metal oxide semiconductor (MOS) transistor comprising:
an active region including a channel region;
a trench insulating isolation region disposed in a substrate and surrounding the active region to define the active region in the substrate;
a gate electrode disposed over the active region without overlapping with the isolation region;
a source region and a drain region disposed in first and second portions of the active region, respectively, the firs…

Assignees

• Sk Hynix Inc

Inventors

• Song Hyun Min

Classifications

• H10W10/031

  Electricity · mapped topic

• H10W10/30

  Electricity · mapped topic

• H10W10/17

  Electricity · mapped topic

• H10W10/014

  Electricity · mapped topic

• H03F2203/45631

  Electricity · mapped topic