Integrated circuit having FinFETS with different fin profiles

Patent metadata

Field	Value
Publication number	US-9583398-B2
Application number	US-201213537770-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jun 29, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile; and
a second FinFET device supported by the substrate, the second FinFET device having a first upper tier and a second upper tier extending from a continuous lower tier, the first upper tier having a different length than the second upper tier, the second FinFET having a tiered fin profile;
wherein a dielectric material extends along sidewalls of the lower tier and between the first upper tier and the second upper tier, an uppermost surface of the dielectric material along sidewalls of the continuous lower tier coplanar with an uppermost surface of the dielectric material between the first upper tier and the second upper tier.

2. The integrated circuit of claim 1 , wherein the first FinFET device is employed in one of a static random access memory cell, a dynamic random access memory cell, a fresh cell, and a static random access memory pull-up transistor.

3. The integrated circuit of claim 1 , wherein the second FinFET device is employed in one of a logic device, a pull-down transistor, and a pass-gate transistor.

4. The integrated circuit of claim 1 , wherein the first FinFET device and the second FinFET device are each p-type metal-oxide-semiconductor field effect transistors.

5. The integrated circuit of claim 1 , wherein the first FinFET device is a p-type metal-oxide-semiconductor field effect transistor employed as a pull up transistor in a first static random access memory and the second FinFET device is an n-type metal-oxide-semiconductor field effect transistor employed as one of a pull down transistor and a pass gate transistor in a second static random access memory.

6. The integrated circuit of claim 1 , wherein the non-tiered fin profile of the first fin is non-uniform over a length of the first fin.

7. The integrated circuit of claim 1 , wherein the first FinFET device is a multiple gate field effect transistor having a plurality of first fins with the non-tiered fin profile.

8. An integrated circuit, comprising:
a substrate;
a first FinFET device supported by the substrate, the first FinFET device having a first fin extending between source and drain regions and disposed beneath a first gate electrode, the first fin including a non-tiered fin profile, a third gate electrode extending over a terminating longitudinal end of the first fin such that the first fin extends from only one sidewall of the third gate electrode in a plan view;
first shallow trench isolations (STIs) along opposing sides of the first fin, an upper surface of the first STIs being planar;
a second FinFET device supported by the substrate, the second FinFET device having a second fin and a third fin extending between source and drain regions and disposed beneath a second gate electrode, the second fin and the third fin including a tiered fin profile comprising an upper tier and a lower tier, the lower tier forming a ledge on opposing sides of the upper tier, wherein the second gate electrode is disposed around only the upper tier of the second fin and the upper tier of the third fin, wherein a longitudinal axis of the upper tier of the second fin and a longitudinal axis of the upper tier of the third fin are substantially parallel along a first direction, the upper tier of the second fin extending along the first direction further than the upper tier of the third fin, the upper tier of the second fin and the upper tier of the third fin extending from a same lower tier; and
second STIs along opposing sides of the second fin, the second STIs extending only partially along sidewalls of the upper tier, an upper surface of the second STIs being planar, the upper surface of the first STIs and the second STIs being coplanar.

9. The integrated circuit of claim 8 , wherein a width of the lower tier of the second fin with the tiered fin profile is at least twice a width of the upper tier of the second fin.

10. The integrated circuit of claim 8 , wherein the non-tiered fin profile of the first fin is non-uniform over a length of the first fin.

11. The integrated circuit of claim 8 , wherein a height of the upper tier of the second fin is less than about fifty nanometers.

12. The integrated circuit of claim 8 , wherein the first FinFET device is formed above a first well with a first doping type and the second FinFET device is formed above a second well with a second doping type different from the first doping type.

13. The integrated circuit of claim 8 , wherein the first FinFET device includes a dummy fin extending between the source and drain regions and disposed beneath the first gate electrode.

14. The integrated circuit of claim 8 , wherein the first FinFET device forms a pull up transistor.

15. The integrated circuit of claim 8 , wherein the second FinFET device forms at least one of a pull down transistor and a pass gate transistor.

16. A method of forming an integrated circuit, comprising:
forming a first FinFET device over a substrate, the first FinFET device having a first fin with a non-tiered fin profile; and
forming a second FinFET over the substrate, the second FinFET having a second fin and a third fin each with a tiered fin profile providing an upper tier and a lower tier, wherein the lower tier forms a step along opposing sides of the upper tier, wherein a longitudinal axis of the upper tier of the second fin and a longitudinal axis of the upper tier of the third fin are substantially parallel along a first direction, the upper tier of the second fin extending along the first direction further than the upper tier of the third fin, the upper tier of the second fin and the upper tier of the third fin extending from a same lower tier;
wherein the forming the first FinFET and the forming the second FinFET comprises, after forming the first fin, the second fin, and the third fin, forming an isolation material adjacent the first fin, the second fin, and the third fin, the isolation material extending between the upper tier of the second fin and the upper tier of the third fin, the isolation material having a planar upper surface.

17. The method of claim 16 , wherein the forming the first FinFET and the forming the second FinFET further comprises forming a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

18. The integrated circuit of claim 1 , wherein the second FinFET includes one or more additional upper tiers extending from the continuous lower tier.

19. The method of claim 16 , wherein a width of the lower tier is at least twice a width of the upper tier.

20. The integrated circuit device of claim 8 , wherein the second FinFET comprises another upper tier on the lower tier.

Assignees

• Liaw Jhon-Jhy
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon-Jhy

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title