Systems and methods for data alignment in a memory system

Patent metadata

Field	Value
Publication number	US-9417802-B1
Application number	US-201514667356-A
Country	US
Kind code	B1
Filing date	Mar 24, 2015
Priority date	Mar 24, 2015
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.

First claim

What is claimed is:

1. A memory system comprising:
a memory controller; and
a memory module communicatively coupled to the memory controller, the memory module comprising:
a plurality of memory chips configured to store data; and
a plurality of memory buffers communicatively coupled to the plurality of memory chips via a plurality of back-side lanes and communicatively coupled to the memory controller via a plurality of front-side lanes;

wherein at least one of the memory controller and the memory module is configured to, alone or in concert with the other:
link train the back-side lanes;
link train the front-side lanes;
determine after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and
responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modify timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds.

2. The memory system of claim 1 , wherein at least one of the memory controller and the memory module is further configured to, alone or in concert with the other:
identify one or more aggressor lanes for the one or more front-side lanes failing to exceed the one or more thresholds; and
modify timing of data in the one or more aggressor lanes in order to improve signal integrity of one or more of the one or more front-side lanes failing to exceed the one or more thresholds.

3. The memory system of claim 1 , wherein the memory module is coupled to the memory controller via a multi-drop bus.

4. The memory system of claim 1 , wherein the memory module comprises double data rate memory.

5. The memory system of claim 1 , wherein the plurality of memory chips comprises dynamic random access memory.

6. The memory system of claim 1 , wherein a bit width of the front-side lanes is greater than a bit width of the back-side lanes.

7. The memory system of claim 6 , wherein the bit width of the front-side lanes is twice than the bit width of the back-side lanes.

8. A method comprising:
link training a plurality of back-side lanes communicatively coupling a plurality of memory chips integral to a memory module to a plurality of data buffers integral to the memory module;
link training a plurality of front-side lanes communicatively coupling the plurality of data buffers to a memory controller;
determining after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and
responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds.

9. The method of claim 8 , further comprising:
identifying one or more aggressor lanes for the one or more front-side lanes failing to exceed the one or more thresholds; and
modifying timing of data in the one or more aggressor lanes in order to improve signal integrity of one or more of the one or more front-side lanes failing to exceed the one or more thresholds.

10. The method of claim 8 , wherein the memory module is coupled to the memory controller via a multi-drop bus.

11. The method of claim 8 , wherein the memory module comprises double data rate memory.

12. The method of claim 8 , wherein the plurality of memory chips comprises dynamic random access memory.

13. The method of claim 8 , wherein a bit width of the front-side lanes is greater than a bit width of the back-side lanes.

14. The method of claim 13 , wherein the bit width of the front-side lanes is twice than the bit width of the back-side lanes.

15. An information handing system, comprising:
a processor; and
a memory system comprising:
a memory controller; and
a memory module communicatively coupled to the memory controller, the memory module comprising:
a plurality of memory chips configured to store data; and
a plurality of memory buffers communicatively coupled to the plurality of memory chips via a plurality of back-side lanes and communicatively coupled to the memory controller via a plurality of front-side lanes;
wherein at least one of the memory controller and the memory module is configured to, alone or in concert with the other:
link train the back-side lanes;
link train the front-side lanes;
determine after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and
responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modify timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds.

16. The information handling system of claim 15 , wherein at least one of the memory controller and the memory module is further configured to, alone or in concert with the other:
identify one or more aggressor lanes for the one or more front-side lanes failing to exceed the one or more thresholds; and
modify timing of data in the one or more aggressor lanes in order to improve signal integrity of one or more of the one or more front-side lanes failing to exceed the one or more thresholds.

17. The information handling system of claim 15 , wherein the memory module is coupled to the memory controller via a multi-drop bus.

18. The information handling system of claim 15 , wherein the memory module comprises double data rate memory.

19. The information handling system of claim 15 , wherein the plurality of memory chips comprises dynamic random access memory.

20. The information handling system of claim 15 , wherein a bit width of the front-side lanes is greater than a bit width of the back-side lanes.

21. The information handling system of claim 20 , wherein the bit width of the front-side lanes is twice than the bit width of the back-side lanes.

22. The information handling system of claim 15 , wherein the memory controller is integral to the processor.

Assignees

• Dell Products Lp

Inventors

• Berke Stuart Allen
• Mutnury Bhyrav M
• Sankaranarayanan Vadhiraj

Classifications

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title