Vertical memory devices

Patent metadata

Field	Value
Publication number	US-9425208-B2
Application number	US-201514682567-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Apr 17, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure, the gate structure including a transistor;
a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate;
a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels; and
a blocking structure between the cell region and the peripheral circuit region, a height of the blocking structure being greater than a height of the gate structure in the peripheral circuit region.

2. The vertical memory device of claim 1 , wherein
the gate lines extend in a second direction that is parallel with respect to the top surface of the substrate, and
the blocking structure extends in at least a third direction that is parallel with respect to the top surface of the substrate and crosses the second direction.

3. The vertical memory device of claim 2 , wherein the blocking structure includes a dummy channel having a material that is the same as that of the channel.

4. The vertical memory device of claim 1 , further comprising;
a dielectric layer structure on each of the outer sidewalls of the channels,
wherein the blocking structure includes a dummy dielectric layer having a material that is the same as that of the dielectric layer structure.

5. The vertical memory device of claim 1 , wherein the blocking structure includes an air gap.

6. The vertical memory device of claim 1 , wherein the blocking structure includes:
at least one dummy channel column including a plurality of dummy channel structures.

7. The vertical memory device of claim 1 , further comprising;
contacts electrically connected to the gate lines on the cell region,
wherein the blocking structure includes at least one dummy contact column, and
the at least one dummy contact column includes a plurality of dummy contacts.

8. The vertical memory device of claim 1 , wherein the blocking structure includes a dummy conductive line, the dummy conductive line contacting the top surface of the substrate.

9. The vertical memory device of claim 8 , further comprising:
a common source line on the cell region,
wherein the common source line and the dummy conductive line include the same conductive material.

10. The vertical memory device of claim 1 , wherein the blocking structure is at least partially buried in the substrate.

11. The vertical memory device of claim 10 , wherein the gate structure includes a gate electrode buried in the substrate.

12. A vertical memory device, comprising:
a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure, the gate structure including a transistor;
a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate;
a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels;
a common source line on the cell region; and
a blocking structure between the cell region and the peripheral circuit region, the blocking structure surrounding the cell region, a height of the blocking structure being greater than a height of the gate structure in the peripheral circuit region.

13. The vertical memory device of claim 12 , wherein the blocking structure includes a dummy channel having a material the same as that of the channel.

14. The vertical memory device of claim 12 , wherein the blocking structure includes at least one dummy channel column having a shape that is the same as that of the channels.

15. The vertical memory device of claim 12 , wherein the blocking structure has a material that is the same as that of the common source line.

16. The vertical memory device of claim 15 , further comprising;
a separation layer pattern formed on both sidewalls of the common source line facing each other,
wherein the blocking structure includes,
a dummy conductive line having a conductive material that is the same as that of the common source line, and
a dummy separation layer pattern formed on both sidewalls of the dummy conductive line facing each other, and
the dummy separation layer pattern includes an insulation material that is the same as that of the separation layer pattern.

17. The vertical memory device of claim 12 , wherein
the common source line extends in a second direction that is parallel with respect to the top surface of the substrate, and
the blocking structure extends in at least a third direction that is parallel with respect to the top surface of the substrate and crosses the second direction.

18. A vertical memory device, comprising:
a substrate including a cell region, a blocking region and a peripheral circuit region, the peripheral circuit region including a gate structure, the gate structure including a transistor;
a gate line structure on the cell region, the gate line structure including
a plurality of insulating interlayer patterns and a plurality of gate lines alternately stacked in a first direction that is vertical with respect to a top surface of the substrate,
a plurality of channels extending through the plurality of insulating interlayer patterns and the plurality of gate lines;

a peripheral circuit on the peripheral circuit region; and
a blocking structure on the blocking region, the blocking structure defining a boundary between the gate line structure and the peripheral circuit region, a height of the blocking structure being greater than a height of the gate structure in the peripheral circuit region.

19. The vertical memory device of claim 18 , wherein
the gate line structure extends in a second direction that is parallel with respect to the top surface of the substrate, and
a plurality of the gate line structures are arranged in a third direction that is parallel with respect to the top surface of the substrate and crosses the second direction.

20. The vertical memory device of claim 19 , wherein the blocking structure extends in the third direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hong-Soo
• Hur Sung-Hoi
• Chin So-Wi

Classifications

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic