Sram cells with vertical gate-all-round mosfets

Patent metadata

Field	Value
Publication number	US-2016133633-A1
Application number	US-201514982556-A
Country	US
Kind code	A1
Filing date	Dec 29, 2015
Priority date	Sep 15, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A Static Random Access Memory (SRAM) cell includes a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate as a second source/drain region. A first isolated active region is in the SRAM cell and acts as the bottom plate of the first pull-down transistor and the bottom plate of the first pass-gate transistor. A second isolated active region is in the SRAM cell and acts as the bottom plate of the second pull-down transistor and the bottom plate of the second pass-gate transistor.

First claim

What is claimed is:

1 . A Static Random Access Memory (SRAM) cell comprising:
a first pull-up transistor and a second pull-up transistor; a first pull-down transistor and a second pull-down transistor electrically coupled to the first pull-up transistor and the second pull-up transistor; a first pass-gate transistor and a second pass-gate transistor, wherein each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors comprises a first source/drain region, a channel over the first source/drain region, and a second source/drain region over the channel; and a first isolated active region, wherein the first isolated active region acts as both the first source/drain region of the first pull-down transistor and the first source/drain region of the first pass-gate transistor.

2 . The SRAM cell of claim 1 , wherein the first isolated active region is within the SRAM cell, and is spaced apart from all boundaries of the SRAM cell.

3 . The SRAM cell of claim 1 , wherein the first isolated active region is fully encircled by isolation regions in the SRAM cell.

4 . The SRAM cell of claim 1 further comprising:
an additional active region extending to opposite boundaries of the SRAM cell, wherein the additional active region acts as a source region of the first pull-up transistor and a source region of the second pull-up transistor.

5 . The SRAM cell of claim 4 , wherein the additional active region is a CVdd power node.

6 . The SRAM cell of claim 1 further comprising:
a second isolated active region, wherein the second isolated active region acts as both the first source/drain region of the second pull-down transistor and the first source/drain region of the second pass-gate transistor.

7 . The SRAM cell of claim 1 further comprising a butted contact connecting the first isolated active region to a common gate electrode of the second pull-up transistor and the second pull-down transistor.

8 . The SRAM cell of claim 7 , wherein the butted contact is further connected to a top plate contact, and the top plate contact is over and contacts the second source/drain region of the first pull-up transistor.

9 . A Static Random Access Memory (SRAM) cell comprising:
a semiconductor substrate; a first boundary and a second boundary opposite to each other; a first pull-up transistor and a second pull-up transistor; a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor; a first pass-gate transistor and a second pass-gate transistor, wherein each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors comprise a first source/drain region, a channel over the first source/drain region, and a second source/drain region over the channel; and a continuous active region in the semiconductor substrate and extending from the first boundary to the second boundary, wherein the continuous active region acts as both the first source/drain region of the first pull-up transistor and the first source/drain region of the second pull-up transistor.

10 . The SRAM cell of claim 9 further comprising:
a first isolated active region in the SRAM cell, wherein the first isolated active region acts as both the first source/drain region of the first pull-down transistor and the first source/drain region of the first pass-gate transistor, and acts as a data storage node of the SRAM cell, and wherein the first isolated active region is spaced apart from all boundaries of the SRAM cell.

11 . The SRAM cell of claim 10 further comprising:
a second isolated active region in the SRAM cell, wherein the first isolated active region acts as both the first source/drain region of the second pull-down transistor and the first source/drain region of the second pass-gate transistor, and wherein the second isolated active region is spaced apart from all boundaries of the SRAM cell.

12 . The SRAM cell of claim 9 further comprising:
a first CVdd metal line over the SRAM cell and connected to the continuous active region;
a first CVss metal line and a second CVss metal line parallel to, and on opposite sides of, the first CVdd metal line;
a first bit-line and a second bit-line parallel to, and on opposite sides of, the first CVdd metal line; and
a word-line perpendicular to the first CVdd metal line, the first and the second CVss metal lines, and the first and the second bit-lines.

13 . A Static Random Access Memory (SRAM) cell comprising:
a first pull-up transistor and a second pull-up transistor; a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor; a first pass-gate transistor and a second pass-gate transistor, wherein each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors comprises a first source/drain region, a channel over the first source/drain region, and a second source/drain region over the channel; a first isolated active region, wherein the first isolated active region acts as both the first source/drain region of the first pull-up transistor and the first source/drain region of the first pass-gate transistor; and a butted contact connecting the first isolated active region to gate electrodes of the second pull-up transistor and the second pull-down transistor.

14 . The SRAM cell of claim 13 further comprising a second isolated active region, wherein the second isolated active region acts as both the first source/drain region of the second pull-up transistor and the first source/drain region of the second pass-gate transistor.

15 . The SRAM cell of claim 13 , wherein the first isolated active region is within the SRAM cell, and is spaced apart from all boundaries of the SRAM cell.

16 . The SRAM cell of claim 13 , wherein the first isolated active region is fully encircled by an isolation region in the SRAM cell.

17 . The SRAM cell of claim 13 further comprising:
an additional active region in the SRAM cell, wherein the additional active region acts as source regions of both the first pull-down transistor and the second pull-down transistor.

18 . The SRAM cell of claim 17 further comprising a first boundary and a second boundary opposite to each other, wherein the additional active region extends from the first boundary to the second boundary.

19 . The SRAM cell of claim 17 , wherein the additional active region is a CVss power node.

20 . The SRAM cell of claim 13 , wherein the butted contact is further connected to a top plate contact, and the top plate contact is over and contacts the second source/drain region of the first pull-up transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D64/251 Primary

  Source or drain electrodes for field-effect devices · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title