Partial Block Erase For Open Block Reading In Non-Volatile Memory

Patent metadata

Field	Value
Publication number	US-2016172045-A1
Application number	US-201514794242-A
Country	US
Kind code	A1
Filing date	Jul 8, 2015
Priority date	Dec 10, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.

First claim

What is claimed is:

1 . A non-volatile storage device, comprising:
a block of non-volatile storage elements including a set of word lines; and managing circuitry in communication with the block of non-volatile storage elements, the managing circuitry is configured to receive a programming request associated with a second subset of the word lines of the block after reading from one or more word lines of a first subset of the word lines of the block, the managing circuitry is configured to verify the second subset of word lines for an erased state prior to programming the second subset, the managing circuitry is configured to erase the second subset of word lines while inhibiting the first subset of word lines from being erased in response to verifying that the second subset of word lines are not in the erased state.

2 . The non-volatile storage device of claim 1 , wherein:
the programming request is a second programming request; the managing circuitry is configured to erase the block of non-volatile storage elements in response to a first programming request associated with the first subset of word lines; the managing circuitry is configured to program the first subset of word lines after erasing the block of non-volatile storage elements; the managing circuitry is configured to respond to a read request by reading from the one or more word lines of the first subset of word lines after programming the first subset.

3 . The non-volatile storage device of claim 1 , wherein:
the managing circuitry is configured to determine in response to the programming request, a number of read operations associated with the first subset of word lines since programming the first subset of word lines; and the managing circuitry is configured to verify the second subset of word lines for the erased state in response to determining that the number of read operations is above a threshold number of read operations.

4 . The non-volatile storage device of claim 1 , wherein:
the managing circuitry is configured to verify the second subset of word lines for the erased state in response to the programming request.

5 . The non-volatile storage device of claim 1 , wherein:
the managing circuitry is configured to erase the second subset of word lines using a weak erase configured to only partially erase non-volatile storage elements of the second subset of word lines.

6 . The non-volatile storage device of claim 5 , wherein:
the managing circuitry is configured to store in response to verifying that the second subset of word lines are not in the erased state, an indication that one or more pages of the second subset of word lines should not be programed until the block is erased.

7 . The non-volatile storage device of claim 6 , wherein:
the indication indicates that one or more lower pages of the second subset of word lines should not be programmed; the managing circuitry is configured to program one or more upper pages of the second subset of word lines with user data in response to the indication; and the managing circuitry is configured to program the one or more lower pages of the second subset of word line with dummy data in response to the indication.

8 . The non-volatile storage device of claim 1 , wherein:
the block of non-volatile storage elements includes a plurality of NAND strings of non-volatile storage elements that are coupled to each of the word lines of the block; and the managing circuitry is configured to erase the second subset of word lines while inhibiting the first subset of word lines from being erased by erasing a second set of non-volatile storage elements from each of the NAND strings of the block while inhibiting a first set of non-volatile storage elements from each of the NAND strings of the block from being erased.

9 . The non-volatile storage device of claim 8 , wherein the managing circuitry is configured to erase the second subset of word lines while inhibiting the first subset of word lines from being erased by:
providing a first positive voltage to the first subset of word lines; providing a second positive voltage lower than the first positive voltage or zero volts to the second subset of word lines; and providing a third positive voltage to the plurality of NAND strings, the third positive voltage.

10 . The non-volatile storage device of claim 9 , wherein:
the plurality of NAND strings are formed in a two dimensional memory array using a substrate; and the managing circuitry is configured to provide the third positive voltage to the plurality of NAND strings by applying one or more positive erase voltage pulses to a well formed in the substrate for the plurality of NAND strings.

11 . The non-volatile storage device of claim 9 , wherein:
the plurality of NAND strings are vertical NAND strings in a three dimensional memory array formed above a substrate; the plurality of NAND string are coupled to a plurality of bit lines; and the managing circuitry is configured to provide the third positive voltage to a channel for each of the NAND strings of the plurality of NAND strings by applying one or more positive erase voltage pulses to the plurality of bit lines.

12 . A method, comprising:
receiving a programming request associated with a second subset of word lines of a block of non-volatile storage elements, the second subset of word lines has not been programmed since a last erase operation and the block of non-volatile storage elements includes a first subset of word lines that has been programmed since the last erase operation; prior to programming the second subset of word lines, verifying the second subset of word lines for an erased state; and in response to verifying that the second subset of word lines is not in the erased state, storing an indication that one or more pages of the second subset of word lines should not be programed until the block is erased.

13 . The method of claim 12 , wherein the indication indicates that a lower page of the second subset of word lines should not be programmed, the method further comprising:
programming an upper page of the second subset of word lines with user data; and programming the lower page of the second subset of word line with dummy data.

14 . The method of claim 12 , wherein the indication indicates that all pages of the second subset of word lines should not be programmed, the method further comprising:
determining one or more alternate blocks for fulfilling the programming request associated with the second subset of the word lines of the block.

15 . A method, comprising:
performing one or more read operations for a first subset of word lines of a block of non-volatile storage elements, the first subset of word lines including non-volatile storage elements that have been programmed since a previous erase operation for the block of non-volatile storage elements, the block of non-volatile storage elements including a second subset of word lines including non-volatile storage elements that have not been programmed since the previous erase operation; after performing the one or more read operations for the first subset of word lines, receiving a programming request associated with the second subset of word lines of the block; prior to programming the second subset of word lines, verifying the second subset of word lines for an erased state; and in response to verifying that the second subset of word lines are not in the erased state, erasing the second subset of word lines while inhibiting the first subset of word lines from being erased.

16 . The method of claim

Assignees

• Sandisk Technologies Inc

Inventors

• Shukla Pitamber
• Chin Henry
• Lee Dana
• Hsu Cynthia

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title