Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory

Patent metadata

Field	Value
Publication number	US-2016111164-A1
Application number	US-201414518340-A
Country	US
Kind code	A1
Filing date	Oct 20, 2014
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.

First claim

1 . A method for operating a memory device, comprising:
performing a programming operation involving a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer, a control gate, a drain, a source and a channel, and the performing the programming operation comprises configuring the memory cells to provide a positive gate-to-channel voltage for the memory cells, the configuring the memory cells to provide the positive gate-to-channel voltage comprises applying a program voltage to the control gates of the memory cells; in response to completion of the programming operation, performing a data retention operation which configures the memory cells to provide a negative gate-to-channel voltage for the memory cells; wherein:
the memory cells are in NAND strings;
the NAND strings comprise drain-side select gate transistors; and
the configuring the memory cells to provide the negative gate-to-channel voltage comprises applying a drain voltage to drains of the drain-side select gate transistors and a control gate voltage to control gates of the drain-side select gate transistors which cause the drain-side select gate transistors to charge up the channels by gate-induced drain leakage; and
performing an erase operation for the set of memory cells, the performing the erase operation comprises applying a drain voltage to the drains of the drain-side select gate transistors and a control gate voltage to the control gates of the drain-side select gate transistors which cause the drain-side select gate transistors to charge up the channels by gate-induced drain leakage, wherein the drain voltage applied to the drains of the drain-side select gate transistors in the data retention operation is lower than the drain voltage applied to the drains of the drain-side select gate transistors in the erase operation.

2 . (canceled)

3 . The method of claim 1 , wherein:
the channels of the memory cells extend in vertical pillars.

4 . (canceled)

5 . The method of claim 1 , wherein:
the drain voltage applied to the drains of the drain-side select gate transistors in the data retention operation is 30-70% of the drain voltage applied to the drains of the drain-side select gate transistors in the erase operation.

6 . The method of claim 1 , wherein:
the drain voltage applied to the drains of the drain-side select gate transistors in the erase operation is stepped up in magnitude using incremental step pulse erasing, starting from an initial voltage and ending at a final voltage; and the drain voltage applied to the drains of the drain-side select gate transistors in the data retention operation is 30-70% of the final voltage.

7 . The method of claim 1 , wherein:
the memory cells are connected to different word lines in the memory device; the completion of the programming operation occurs when programming is completed for the memory cells connected to the different word lines; and the data retention operation is performed concurrently for the memory cells connected to the different word lines.

8 . The method of claim 1 , wherein:
the memory cells are connected to different word lines in a block; the completion of the programming operation occurs when programming is completed for the block; and the data retention operation is performed concurrently for the memory cells connected to the different word lines.

9 . (canceled)

10 . The method of claim 1 , wherein:
a magnitude of the negative gate-to-channel voltage is relatively smaller when a number of program-erase cycles in the memory device is relatively larger.

11 . The method of claim 1 , wherein:
the configuring the memory cells to provide the positive gate-to-channel voltage comprises repeatedly applying the program voltage to the control gates of the memory cells using incremental step pulse programming.

12 . (canceled)

13 . (canceled)

14 . (canceled)

15 . A memory device, comprising:
a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer; a set of word lines, the memory cells are connected to different word lines of the set of word lines; and a control circuit, the control circuit configured to:
perform an erase operation for the set of memory cells using an erase voltage, the erase operation provides a negative gate-to-channel voltage for the memory cells,
after the erase operation, perform a programming operation for the set of memory cells using a program voltage, the programming operation provides a positive gate-to-channel voltage for the memory cells, and
after the programming operation, perform a data retention operation using a weak erase voltage, weaker than the erase voltage of the erase operation, the data retention operation provide a negative gate-to-channel voltage for the memory cells which is configured to increase a data retention of the memory cells, wherein:
the control circuit, to provide the negative gate-to-channel voltage during the erase operation, is configured to ground control gate voltages for the memory cells while boosting channels of the memory cells;
the control circuit, to provide the negative gate-to-channel voltage during the data retention operation, is configured to ground the control gate voltages for the memory cells while boosting channels of the memory cells; and
the channels are boosted to a higher level during the erase operation than during the data retention operation.

16 . The memory device of claim 15 , wherein:
a magnitude of the weak erase voltage is less than 30-70% of a magnitude of the erase voltage of the erase operation.

17 . The memory device of claim 15 , wherein:
the erase operation uses a plurality of erase voltages, starting from an initial voltage and ending at a final voltage, wherein the weak erase voltage is less than 30-70% of a magnitude of the final voltage of the erase operation.

18 . The memory device of claim 15 , wherein:
each memory cell of the set of memory cells comprises a tunneling layer adjacent to the charge-trapping layer and a channel layer adjacent to the charge-trapping layer; and the tunneling layer comprises oxide-nitride-oxide.

19 . (canceled)

20 . The memory device of claim 15 , wherein:
the control circuit is configured to boost the channels of the memory cells by gate-induced drain leakage during the erase operation and during the data retention operation.

21 . The memory device of claim 15 , wherein:
the control circuit, to provide the negative gate-to-channel voltage during the erase operation, is configured to provide negative control gate voltages for the memory cells while grounding channels of the memory cells; the control circuit, to provide the negative gate-to-channel voltage during the data retention operation, is configured to provide negative control gate voltages for the memory cells while grounding the channels of the memory cells; and a magnitude of the negative control gate voltage during the erase operation is greater than a magnitude of the negative control gate voltage during the data retention operation.

22 . (canceled)

23 . (canceled)

24 . (canceled)

25 . A method for operating a memory device, comprising:
performing a programming operation involving a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer, a control gate, a drain, a source and a channel, and the performing th

Assignees

• Sandisk Technologies Inc

Inventors

• Chen hong-yan
• Dong Yingda
• Lu Ching-Huang

Classifications

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3413

  Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step · CPC title

• G11C16/3409

  Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step · CPC title