Circuit and method for design of RF integrated circuits for process control monitoring

Patent metadata

Field	Value
Publication number	US-10817644-B2
Application number	US-201816165167-A
Country	US
Kind code	B2
Filing date	Oct 19, 2018
Priority date	Oct 19, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

The present disclosure relates to testing structures and, more particularly, to a circuit and method for design of RF integrated circuits for process control monitoring. The circuit includes a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.

First claim

What is claimed:

1. A circuit comprising:
a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and
a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.

2. The circuit of claim 1 , wherein the plurality of NFET switches are NFETS and gate (DG) NFETs.

3. The circuit of claim 2 , wherein:
the NFETs are in series connection;
the DGFETs are in series connection; and
the NFETs are in series connection with a first of the DGFETs and in parallel connection with a second of the DGFETs.

4. The circuit of claim 2 , wherein the plurality of active devices include a DGNFET and the switches are configurable to isolate the DGNFET by turning it on and off.

5. The circuit of claim 4 , wherein the active devices further include a NFET in series with the DGNFET.

6. The circuit of claim 5 , wherein the switches are configurable to isolate the NFET of the active devices by turning it on and off.

7. The circuit of claim 6 , wherein the switches are NFETs.

8. The circuit of claim 7 , wherein the switches are in a series connection.

9. The circuit of claim 8 , wherein the switches are in a parallel connection with the NFET and the DGNFET of the circuit.

10. The circuit of claim 1 , wherein the active devices and the passive devices are arranged to be a low noise amplifier.

11. The circuit of claim 1 , wherein the active devices and the passive devices are configurable into eight (8) different topographies by switching on and off different combinations of the switches.

12. A circuit comprising:
a low noise amplifier (LNA) comprising a plurality of active devices and passive devices; and
a plurality of NFETs and double gate (DG) NFETs connected to the plurality of active devices and passive devices which are configured to turn on and off the active devices and passive devices to provide built-in different circuit topologies of the LNA, wherein:
the NFETs are in series connection;
the DGFETs are in series connection; and
the NFETs are in series connection with a first of the DGFETs and in parallel connection with a second of the DGFETs.

13. The circuit of claim 12 , wherein the active devices include a DGNFET and a NFET in series, and the switches are configurable to isolate either the DGNFET or the NFET of the active devices.

14. The circuit of claim 13 , wherein the passive devices include inductors and capacitors.

15. The circuit of claim 12 , wherein the active devices and the passive devices are configurable into eight (8) different topographies by switching on and off different combinations of the switches.

16. The circuit of claim 12 , wherein the active devices and the passive devices are configurable into eight (8) different topographies by switching on and off different combinations of the switches.

17. The circuit of claim 12 , wherein the active devices include a NFET in series with the DGNFET and the plurality of NFETs and double gate (DG) NFETs are configurable to isolate the NFET of the active devices by turning it on and off.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Gupta Varun
• Lau Wendy Wee Yee
• Goh Szu Huat

Classifications

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F2117/06

  Spare resources, e.g. for permanent fault suppression · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G01R31/2822

  of microwave or radiofrequency circuits (of attenuation, gain, e.g. using network analyzers G01R27/28) · CPC title

• G05B2219/2609

  Process control · CPC title