Programmable optimized band switching LNA for operation in multiple narrow-band frequency ranges

Patent metadata

Field	Value
Publication number	US-9941849-B1
Application number	US-201715430332-A
Country	US
Kind code	B1
Filing date	Feb 10, 2017
Priority date	Feb 10, 2017
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the FEM IC allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

First claim

What is claimed is:

1. An amplifier module comprising:
(a) at least one amplifier having an output transistor configured in a common gate configuration and no more than one input transistor, the input transistor configured in a common source configuration, the amplifier for use in at least two frequency ranges;
(b) an amplifier output;
(c) an amplifier output port;
(d) an output impedance matching network coupled between the amplifier output and the amplifier output port; and
(e) at least one selectable impedance circuit (SIC) comprising: (i) a first and second terminal, the impedance of the at least one SIC being selected from at least two impedance values; and (ii) at least a parallel-coupled output SIC having the first terminal coupled to the amplifier output and the second terminal coupled to the amplifier output port.

2. The amplifier module of claim 1 , wherein the parallel-coupled output SIC includes a capacitor and switch coupled in series between the first and second terminals of the parallel-coupled output SIC.

3. The amplifier module of claim 1 , wherein the parallel-coupled output SIC includes a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

4. The amplifier module of claim 2 , wherein the switch within the SIC is an FET.

5. The amplifier module of claim 1 , wherein the parallel-coupled output SIC further includes at least two legs coupled in parallel between the first and second terminals of the parallel-coupled output SIC, each leg including a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

6. The amplifier module of claim 1 , wherein the amplifier module further includes an amplifier output and wherein the at least one SIC includes at least a shunt-coupled output SIC having the first terminal coupled to the amplifier output and the second terminal coupled to ground.

7. The amplifier module of claim 6 , wherein the shunt-coupled output SIC includes a capacitor and switch coupled in series between the first and second terminals of the parallel-coupled output SIC.

8. The amplifier module of claim 6 , wherein the shunt-coupled output SIC includes a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

9. The amplifier module of claim 7 , wherein the switch within the SIC is an FET.

10. The amplifier module of claim 6 , wherein the parallel-coupled output SIC further includes at least two legs coupled in parallel between the first and second terminals of the parallel-coupled output SIC, each leg including a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

11. The amplifier module of claim 1 , wherein the input transistor has a source and the at least one SIC includes at least an input shunt SIC having the first terminal coupled to a gate of the input transistor and the second terminal coupled to the source of the input transistor.

12. The amplifier module of claim 11 , wherein the input shunt SIC includes a capacitor and switch coupled in series between the first and second terminals of the input shunt SIC.

13. The amplifier module of claim 11 , wherein the input shunt SIC includes a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

14. The amplifier module of claim 13 , wherein the switch within the input shunt SIC is an FET.

15. The amplifier module of claim 11 , wherein the input shunt SIC further includes at least two legs coupled in parallel between the first and second terminals of the input shunt SIC, each leg including a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

16. The amplifier module of claim 1 , wherein the at least one SIC includes at least an input parallel SIC having the first terminal coupled to a gate of the input transistor and the second terminal coupled to ground.

17. The amplifier module of claim 16 , wherein the input parallel SIC includes a capacitor and switch coupled in series between the first and second terminals of the input parallel SIC.

18. The amplifier module of claim 16 , wherein the input parallel SIC includes a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

19. The amplifier module of claim 17 , wherein the switch within the input parallel SIC is an FET.

20. The amplifier module of claim 16 , wherein the input parallel SIC further includes at least two legs coupled in parallel between the first and second terminals of the parallel-coupled output SIC, each leg including a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

21. The amplifier module of claim 1 , wherein the input transistor has a source and the at least one SIC includes at least a degeneration SIC having the first terminal coupled to the source of the input transistor and the second terminal coupled to ground.

22. The amplifier module of claim 21 , wherein the degeneration SIC includes an inductor and switch coupled in series between the first and second terminals of the degeneration SIC.

23. The amplifier module of claim 21 , wherein the degeneration SIC includes a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

24. The amplifier module of claim 22 , wherein the switch within the degeneration SIC is an FET.

25. The amplifier module of claim 21 , wherein degeneration SIC further includes at least two legs coupled in parallel between the first and second terminals of the parallel-coupled output SIC, each leg including a two-port network capable of providing impedance and a switch coupled in series with the two-port network.

26. The amplifier module of claim 1 , further including a bias control module coupled to the gate of the output transistor and configured to provide a bias control signal to the amplifier through the gate of the output transistor.

27. The amplifier module of claim 26 , wherein the at least one SIC includes a control input and wherein the bias control module is further coupled to at least one of the control inputs and configured to provide an impedance selection signal to the at least one SIC.

28. The amplifier module of claim 27 , wherein the bias control module generates the impedance selection signal based on the bias control signal.

29. The amplifier module of claim 27 , wherein the bias control module generates the impedance selection signals and the bias control signal based on the frequency of signals applied to the amplifier module input port.

30. The amplifier module of claim 1 , wherein the amplifier includes at least a first and second branch, the input of the first branch being switchably connected to the input of the second branch.

31. The amplifier module of claim 30 , wherein the first branch of the amplifier includes an input transistor and an output transistor, the input transistor configured as a common source configuration and the output transistor configured in a common gate configuration and the second branch of the amplifier includes a third transistor and a fourth transistor, the third transistor configured in a common source configuration and the fou

Assignees

• Psemi Corp

Inventors

• Ayranci Emre
• Sanner Miles

Classifications

• H04B1/006

  using switches for selecting the desired band (H04B1/0057 takes precedence) · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03H11/28

  Impedance matching networks · CPC title

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F2200/111

  the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not · CPC title