Memory performance when speculation control is enabled, and instruction therefor
US-2015378915-A1 · Dec 31, 2015 · US
US9052890B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9052890-B2 |
| Application number | US-92431110-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 25, 2010 |
| Priority date | Sep 25, 2010 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: an execution logic that includes circuitry to execute instructions; and an instruction execution scheduler logic that includes circuitry coupled with the execution logic, the instruction execution scheduler logic to receive an execute at commit state update instruction, the instruction execution scheduler logic including: at commit state update logic to wait to schedule the execute at commit state update instruction for execution…
Physics · mapped topic
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