Method of manufacturing FinFET with reduced parasitic capacitance and FinFET structure formed thereby

Patent metadata

Field	Value
Publication number	US-10811409-B2
Application number	US-201816161620-A
Country	US
Kind code	B2
Filing date	Oct 16, 2018
Priority date	Oct 16, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.

First claim

We claim:

1. A FinFET structure comprising:
a source/drain epitaxial junction on a top surface of each of adjacent fins laterally spaced from one another on a substrate;
a pair of dielectric layers on an upper portion of sidewalls of the adjacent fins and on a lower portion of the source/drain epitaxial junctions on the adjacent fins, wherein one of the pair of dielectric layers extends below the upper portion of the sidewalls of the adjacent fins and is located on a middle portion of the sidewalls of the adjacent fins and extends between the middle portion of the sidewalls of the adjacent fins; and wherein an additional dielectric layer that extends between the middle portion of the sidewalls of the adjacent fins is located on a portion of the one of the pair of dielectric layers that extends between the middle portion of the sidewalls of the adjacent fins;
a metal contact contacting an upper portion of the source/drain epitaxial junctions on the adjacent fins and contacting an upper surface of the additional dielectric layer extending between a middle portion of the sidewalls of the adjacent fins; and
a metal gate perpendicular to the adjacent fins and disposed on a top portion of the adjacent fins not covered by the metal contact.

2. The FinFET structure of claim 1 , further comprising a shallow trench isolation (STI) layer extending between a lower portion of the sidewalls of the adjacent fins, the STI layer being located above the substrate and below the portion of the one of the pair of dielectric layers that extends between the middle portion of the sidewalls of the adjacent fins.

3. The FinFET structure of claim 2 , wherein
an other one of the pair of dielectric layers extends between the upper portion of the sidewalls of the adjacent fins, with the exception of where the metal contact contacts the upper surface of the additional dielectric layer that extends between the middle portion of the sidewalls of the adjacent fins; and
wherein a fourth dielectric layer is located on the other one of the pair of dielectric layers.

4. The FinFET structure of claim 1 , wherein the FinFET has a contact-to-gate parasitic capacitance that is reduced compared to a FinFET not including the metal contact that contacts an upper surface of the additional dielectric layer that extends between the middle portion of the sidewalls of the adjacent fins.

5. The FinFET structure of claim 1 , wherein the metal contact is a via.

6. The FinFET structure of claim 1 , wherein the metal contact comprises W, Co or Ru.

7. The FinFET structure of claim 1 , wherein a distance between the adjacent fins is at least 10 nanometers.

8. The FinFET structure of claim 1 , wherein the metal gate is selected from the group consisting of: HfO 2 , ZrO 2 TiN, TiC, TiAl, TaN W, Co and Ru.

9. The FinFET structure of claim 1 , wherein the source/drain epitaxial junctions comprise a p-doped region and/or an n-doped region.

10. A method of manufacturing a FinFET, comprising:
providing a precursor FinFET structure including a substrate; at least two fins laterally spaced from one another on a top surface of the substrate; a source/drain epitaxial junction on a top surface of each fin; a shallow trench isolation (STI) layer on the top surface of the substrate and between adjacent fins; a first dielectric layer conformally formed on a top surface of the STI layer and sidewalls of the fins located above the top surface of the STI layer and the source/drain epitaxial junctions
forming a conformal second dielectric layer over the first dielectric layer;
removing a portion of second dielectric layer such that the second dielectric layer has a top surface below the top surface of the fins and exposing portion of the first dielectric layer;
forming a conformal third dielectric layer over the second dielectric layer and exposed surfaces of the first dielectric layer;
forming a fourth dielectric layer over third dielectric layer;
removing a portion of fourth dielectric layer such that at least a portion of third dielectric layer between the at least two laterally spaced fins is exposed and such that third dielectric layer located above the at least two laterally spaced fins is also exposed; and
forming a metal contact on the exposed source/drain epitaxial junctions of the at least two adjacent fins and the exposed portion of the second dielectric layer between the at least two adjacent fins.

11. The method of claim 10 , wherein the providing of the precursor FinFET structure includes:
forming the conformal first dielectric layer on the top surface of the STI layer, exposed sidewalls of the fins and exposed surfaces of the source/drain epitaxial junctions, the top surface of the STI layer being below the top surface of the fins.

12. The method of claim 11 , wherein the providing of the precursor FinFET structure further includes:
forming the second dielectric layer on the first dielectric layer such that a top surface of the second dielectric layer is above the top surface of the fins.

13. The method of claim 10 , wherein the precursor FinFET structure further includes at least one sacrificial gate perpendicular to the fins and disposed on and around a portion of the top surface of the fins.

14. The method of claim 13 , wherein the forming of the fourth dielectric layer includes:
forming the fourth dielectric layer on the third dielectric layer,
replacing the at least one sacrificial gate with a metal gate having a cap thereover, and
selectively removing at least a portion of the fourth dielectric layer such that at least a portion of the third dielectric layer located between at least two adjacent fins is exposed and such that the third dielectric layer located above the at least two adjacent fins is exposed.

15. The method of claim 10 , wherein a distance between two adjacent fins under the metal contact is at least 10 nanometers (nm).

16. The method of claim 15 , wherein a thickness of a portion of the metal contact located within the at least 10 nm distance is reduced compared to a FinFET not including the third dielectric layer.

17. The method of claim 10 , wherein the FinFET has a contact-to-gate parasitic capacitance that is reduced compared to a FinFET not including the third dielectric layer.

18. The method of claim 10 , wherein the first dielectric layer comprises one or more of SiN, SiNC, SiNOC, SiBCN, Si 3 N 4 , SiCO and SiO 2 .

Assignees

• Globalfoundries Inc

Inventors

• Shu Jiehui
• Zang Hui
• Xu Guowei
• Gao Jian

Classifications

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title