Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10522368-B2
Application number	US-201816049138-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Feb 18, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;
a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction; and
a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer, wherein:
the semiconductor device is an n-channel semiconductor field effect transistor,
the source/drain structure includes a SiP layer, and
an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

2. The semiconductor device of claim 1 , wherein an amount of phosphorous in the SiP layer is in a range from 1×10 20 cm −3 to 5×10 21 cm −3 .

3. The semiconductor device of claim 1 , wherein the alloy layer is in contact with the SiP layer.

4. The semiconductor device of claim 1 , wherein the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

5. The semiconductor device of claim 4 , wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

6. The semiconductor device of claim 5 , wherein the amount of phosphorous in the first SiP layer is in a range from 2×10 20 cm −3 to 7×10 20 cm −3 , and the amount of phosphorous in the second SiP layer is in a range from 3×10 20 cm −3 to 4×10 21 cm −3 .

7. A semiconductor device including an n-type FET, the n-type FET comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer; and
a source/drain structure formed on the upper portion of the fin structure, wherein:
the source/drain structure includes a SiP layer and a SiGe layer disposed over the SiP layer and an alloy layer of Si, Ge and Ti disposed over the SiGe layer.

8. The semiconductor device of claim 7 , wherein the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

9. The semiconductor device of claim 8 , wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

10. The semiconductor device of claim 9 , wherein the amount of phosphorous in the first SiP layer is in a range from 2×10 20 cm −3 to 7×10 20 cm −3 , and the amount of phosphorous in the second SiP layer is in a range from 3×10 20 cm −3 to 4×10 21 cm −3 .

11. The semiconductor device of claim 7 , wherein the SiGe layer is a Si 1-x Ge x layer, where x is in a range from 0.25 to 0.5.

12. The semiconductor device of claim 11 , wherein the SiGe layer further contains phosphorous.

13. The semiconductor device of claim 12 , wherein an amount of phosphorus in the Si 1-x Ge x layer is in a range from 1×10 20 cm −3 to 5×10 21 cm −3 .

14. A semiconductor device including an n-type FET, the n-type FET comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;
a source/drain structure formed on the upper portion of the fin structure; and
a source/drain contact disposed over the source/drain structure, wherein:
the source/drain structure includes a SiP layer,
a layer containing Si and Ge is formed over the SiP layer,
an upper part of the layer is an alloy layer of Si, Ge and Ti and is in contact with the source/drain contact, and
a lower part of the layer containing Si and Ge not in contact with the source/drain contact is a Si 1-x Ge x layer without Ti.

15. The semiconductor device of claim 14 , wherein the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

16. The semiconductor device of claim 15 , wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

17. The semiconductor device of claim 14 , wherein the amount of phosphorous in the first SiP layer is in a range from 2×10 20 cm −3 to 7×10 20 cm −3 , and the amount of phosphorous in the second SiP layer is in a range from 3×10 20 cm −3 to 4×10 21 cm −3 .

18. The semiconductor device of claim 14 , wherein x in the Si 1-x Ge x layer is in a range from 0.25 to 0.5.

19. The semiconductor device of claim 14 , wherein the Si 1-x Ge x layer further contains phosphorous, and an amount of phosphorus in the Si 1-x Ge x layer is in a range from 1×10 20 cm −3 to 5×10 21 cm −3 .

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chao Yuan-Shun
• Kuo Chih-Wei

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L29/66969

  Electricity · mapped topic

• H01L29/26

  Electricity · mapped topic

• H01L29/45

  Electricity · mapped topic