Devices and methods of forming unmerged epitaxy for finfet device

Patent metadata

Field	Value
Publication number	US-2016365451-A1
Application number	US-201514735283-A
Country	US
Kind code	A1
Filing date	Jun 10, 2015
Priority date	Jun 10, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

First claim

What is claimed is:

1 . A method comprising:
obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin.

2 . The method of claim 1 , further comprising:
depositing a first interlayer dielectric layer over the wafer; planarizing the first interlayer dielectric layer; etching to expose at least a portion of the first layer of an epitaxial growth; and forming at least one second layer of an epitaxial growth on the first layer of an epitaxial growth.

3 . The method of claim 1 , wherein the first layer of an epitaxial growth substantially takes on a shape of a diamond.

4 . The method of claim 2 , wherein the at least one second layer of an epitaxial growth substantially takes on a shape of at least one of a diamond, a square, a rectangle, a pentagon, a trapezoid, and a polygon.

5 . The method of claim 1 , wherein the first layer of an epitaxial growth is conformally formed over the at least one fin.

6 . The method of claim 2 , further comprising:
depositing at least one barrier layer over the at least one second layer of an epitaxial growth; depositing at least one flowable oxide layer; planarizing the at least one flowable oxide layer; performing replacement metal gate process on the at least one sacrificial gate structure; depositing at least one second interlayer dielectric layer over the at least one flowable oxide layer; performing lithography to the at least one second interlayer dielectric layer; and etching to expose at least a portion of the at least one second layer of an epitaxial growth.

7 . The method of claim 6 , further comprising:
forming a first contact region over the at least one source and a second contact region over the at least one drain.

8 . The method of claim 6 , wherein the at least one barrier layer is a contact etch stop layer.

9 . The method of claim 8 , wherein the contact etch stop layer comprises:
nitride; and low k material.

10 . The method of claim 6 , further comprising:
depositing the at least one barrier layer over the first interlayer dielectric layer.

11 . The method of claim 2 , further comprising:
depositing a second interlayer dielectric layer over the at least one second layer of an epitaxial growth; planarizing the second interlayer dielectric layer; etching to expose at least a portion of the at least one second layer of the epitaxial growth; and forming at least one third layer of an epitaxial growth on the at least one second layer of an epitaxial growth.

12 . The method of claim 11 , further comprising:
depositing at least one barrier layer over the at least one third layer of an epitaxial growth; depositing at least one third interlayer dielectric layer over the at least one barrier layer; planarizing the at least one third interlayer dielectric layer; etching to expose at least a portion of the at least one third layer of an epitaxial growth; and forming a first contact region over the at least one source and a second contact region over the at least one drain.

13 . The method of claim 11 , wherein the at least one third layer of an epitaxial growth substantially takes on a shape of at least one of a diamond, a square, a rectangle, a pentagon, a trapezoid, and a polygon.

14 . The method of claim 12 , further comprising:
depositing the at least one barrier layer over the second interlayer dielectric layer.

15 . The method of claim 12 , wherein the at least one barrier layer is a contact etch stop layer comprising:
nitride; and low k material.

16 . A semiconductor device comprising:
a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

17 . The device of claim 16 , further comprising:
at least one third layer of an epitaxial growth superimposing the at least one second layer of an epitaxial growth.

18 . The device of claim 16 , wherein the first layer of an epitaxial growth substantially takes on a shape of a diamond.

19 . The device of claim 16 , wherein the at least one second layer of an epitaxial growth substantially takes on a shape of at least one of a diamond, a square, a rectangle, a pentagon, a trapezoid, and a polygon.

20 . The device of claim 17 , wherein the at least one third layer of an epitaxial growth substantially takes on a shape of at least one of a diamond, a square, a rectangle, a pentagon, a trapezoid, and a polygon.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Liu Bingwu

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H01L21/31051

  Electricity · mapped topic