Semiconductor devices with post-probe configurability

Patent metadata

Field	Value
Publication number	US-10811372-B2
Application number	US-201916416210-A
Country	US
Kind code	B2
Filing date	May 18, 2019
Priority date	Nov 13, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.

First claim

We claim:

1. A semiconductor device assembly, comprising:
a substrate;
a die coupled to the substrate, the die including:
a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element,
a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements,
a third contact pad electrically coupled to a third circuit on the die including only passive circuit elements, and
a plated pad directly overlying and electrically coupling at least a part of the first contact pad, at least a part of the second contact pad, and at least a part of the third contact pad;

wherein the substrate includes a substrate contact electrically coupled to the plated pad on the die.

2. The semiconductor device assembly of claim 1 , wherein the first circuit is a driver circuit.

3. The semiconductor device assembly of claim 1 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

4. The semiconductor device assembly of claim 1 , wherein the substrate contact is electrically coupled to the plated pad by a wirebond.

5. The semiconductor device assembly of claim 1 , wherein the die is a NAND memory die.

6. A semiconductor device assembly, comprising:
a substrate including a substrate contact; and
a plurality of semiconductor dies, each including:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element,
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements, and
a third contact pad electrically coupled to a third circuit on the semiconductor die including only passive circuit elements;

wherein the first contact pads of all of the plurality of semiconductor dies are electrically coupled to the substrate contact, and
wherein at least one of the plurality of semiconductor dies further includes a plated pad directly overlying and electrically coupling at least a part of the first contact pad at least a part of the second contact pad, and at least a part of the third contact pad.

7. The semiconductor device assembly of claim 6 , wherein the first circuit of each of the plurality of semiconductor dies is a driver circuit.

8. The semiconductor device assembly of claim 6 , wherein the second circuit of each of the plurality of semiconductor dies includes one or more capacitors to provide electrostatic discharge (ESD) protection.

9. The semiconductor device assembly of claim 6 , wherein the plurality of semiconductor dies comprise NAND memory dies.

10. The semiconductor device assembly of claim 6 , wherein the plurality of semiconductor dies comprises more than two semiconductor dies.

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Duesman Kevin G
• Wright Jeffrey P
• Boyer Warren L

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title