Stack packages relating to bridge die

Patent metadata

Field	Value
Publication number	US-10811359-B2
Application number	US-201916532772-A
Country	US
Kind code	B2
Filing date	Aug 6, 2019
Priority date	Dec 4, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A stack package includes a first sub-package, a second sub-package stacked on the first sub-package. The first sub-package is configured to include first and second semiconductor dies, a first flexible bridge die disposed between the first and second semiconductor dies.

First claim

What is claimed is:

1. A stack package comprising:
a first flexible substrate and a second flexible substrate which are vertically spaced apart from each other;
a first sub-package disposed between the first and second flexible substrates;
a second sub-package disposed between the first sub-package and the second flexible substrate;
inner connectors electrically connecting the first sub-package to the second sub-package; and
an outer polymeric encapsulating layer filling a space between the first and second flexible substrates to encapsulate the first and second sub-packages,
wherein the first sub-package comprises:
first and second semiconductor dies disposed on the first flexible substrate to be spaced apart from each other;
a first flexible bridge die disposed between the first and second semiconductor dies;
a first inner polymeric encapsulating layer encapsulating the first and second semiconductor dies and the first flexible bridge die;
first redistributed lines electrically connecting the first semiconductor die to the first flexible bridge die; and
second redistributed lines electrically connecting the second semiconductor die to the first flexible bridge die, and
wherein the inner connectors electrically connect the first flexible bridge die to the second sub-package.

2. The stack package of claim 1 , further comprising outer connectors attached to the first flexible substrate,
wherein the first flexible substrate comprises interconnection lines that electrically connect the first flexible bridge die to the outer connectors.

3. The stack package of claim 1 , wherein the second flexible substrate comprises a reinforcement pattern that reinforces stiffness or modulus of elasticity of the second flexible substrate.

4. The stack package of claim 3 , wherein the reinforcement pattern comprises a metal layer.

5. The stack package of claim 1 , wherein the second flexible substrate comprises a polymer layer comprising a polyimide material.

6. The stack package of claim 1 , wherein the first inner polymeric encapsulating layer comprises a silicone resin material.

7. The stack package of claim 1 , wherein the outer polymeric encapsulating layer comprises a silicone resin material.

8. The stack package of claim 1 , wherein the outer polymeric encapsulating layer extends to fill a space between the first and second sub-packages as well as a space between the first sub-package and the first flexible substrate.

9. The stack package of claim 1 , further comprising:
first supporters disposed between the first sub-package and the first flexible substrate to support the first sub-package; and
second supporters disposed between the first sub-package and the second sub-package to be spaced apart from the inner connectors and to support the second sub-package.

10. The stack package of claim 9 ,
wherein the first supporters are polymeric balls attached to both edges of the first sub-package; and
wherein the second supporters are polymeric balls attached to both edges of the second sub-package.

11. The stack package of claim 1 , wherein the first flexible bridge die comprises:
a first flexible bridge die body;
first through vias and second via through vias penetrating the first flexible bridge die body; and
first post bumps and second post bumps connected to top ends of the first and second through vias, respectively, in a one-to-one manner, the first post bumps and second post bumps protruding from a top surface of the first flexible bridge die body.

12. The stack package of claim 11 , wherein the first flexible bridge die body comprises a polyimide layer.

13. The stack package of claim 11 ,
wherein the first redistributed lines extend to electrically connect bottom ends of the first through vias to the first semiconductor die; and
wherein the second redistributed lines extend to electrically connect bottom ends of the second through vias to the second semiconductor die.

14. The stack package of claim 11 , wherein the second sub-package comprises:
third and fourth semiconductor dies disposed on the first sub-package to be spaced apart from each other;
a second flexible bridge die disposed between the third and fourth semiconductor dies and electrically connected to the first and second post bumps;
a second inner polymeric encapsulating layer encapsulating the third and fourth semiconductor dies and the second flexible bridge die;
third redistributed lines electrically connecting the third semiconductor die to the second flexible bridge die; and
fourth redistributed lines electrically connecting the fourth semiconductor die to the second flexible bridge die.

15. The stack package of claim 14 , wherein the second flexible bridge die comprises:
a second flexible bridge die body;
third through vias and fourth through vias penetrating the second flexible bridge die body; and
third post bumps and fourth post bumps connected to top ends of the third and fourth through vias, respectively, in a one-to-one manner, the third and fourth post bumps protruding from a top surface of the second flexible bridge die body.

16. The stack package of claim 15 ,
wherein the third redistributed lines extend to electrically connect bottom ends of the third through vias to the third semiconductor die; and
wherein the fourth redistributed lines extend to electrically connect bottom ends of the fourth through vias to the fourth semiconductor die.

17. The stack package of claim 15 ,
wherein the third through vias are located to overlap with the first through vias in a one-to-one manner; and
wherein the fourth through vias are located to overlap with the second through vias in a one-to-one manner.

18. The stack package of claim 15 ,
wherein the third through vias are located to overlap with the first post bumps in a one-to-one manner; and
wherein the fourth through vias are located to overlap with the second post bumps in a one-to-one manner.

19. A stack package comprising:
a first sub-package;
a second sub-package stacked on the first sub-package;
inner connectors electrically connecting the first sub-package to the second sub-package; and
an outer polymeric encapsulating layer encapsulating the first and second sub-packages,
wherein the first sub-package comprises:
first and second semiconductor dies disposed to be spaced apart from each other;
a first flexible bridge die disposed between the first and second semiconductor dies;
a first inner polymeric encapsulating layer encapsulating the first and second semiconductor dies and the first flexible bridge die;
first redistributed lines electrically connecting the first semiconductor die to the first flexible bridge die; and
second redistributed lines electrically connecting the second semiconductor die to the first flexible bridge die, and
wherein the inner connectors electrically connect the first flexible bridge die to the second sub-package.

20. A stack package comprising:
a first sub-package including first and second semiconductor dies spaced apart from each other by a first flexible bride die disposed between the first and second semiconductor dies, first redistributed lines electrically connecting the first semiconductor die to the first flexible bridge die, and second redistributed line electrically connecting the second semiconductor die to the first flexible bridge die; and
first supporters attached to both edges of the first sub-package.

Assignees

• Sk Hynix Inc

Inventors

• Sung Ki Jun
• Eun Kyoung Tae

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W74/476

  Organic materials comprising silicon · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title