Package substrate having a plurality of chips electrically connected by conductive vias and wiring bonding

Patent metadata

Field	Value
Publication number	US-10079220-B2
Application number	US-201715798698-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Nov 4, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device; a second circuit device disposed in the dielectric body, the second circuit device comprising a third terminal at a top of the second circuit device; a first conductive pillar formed in the dielectric body and connected to the first terminal; a first bonding wire connecting the second terminal and the third terminal; and a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar.

First claim

What is claimed is:

1. A package substrate comprising:
a dielectric body;
a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device;
a second circuit device disposed in the dielectric body and not vertically overlapped with the first circuit device, the second circuit device comprising a third terminal at a top of the second circuit device;
a first conductive pillar formed in the dielectric body and connected to the first terminal;
a first bonding wire connecting the second terminal and the third terminal; and
a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar;
wherein the first and second terminals are located at a first depth of the dielectric body, the third terminal is located at a second depth of the dielectric body, and the first depth is different from the second depth.

2. The package substrate of claim 1 , wherein the first bonding wire is made of gold, silver, copper, palladium, or their combinations.

3. The package substrate of claim 1 , wherein the first circuit device comprises a semiconductor chip or an electronic component, and the second circuit device comprises a semiconductor chip or an electronic component.

4. The package substrate of claim 1 , wherein the second circuit device further comprises a fourth terminal at the top of the second circuit device, the redistribution layer further comprises a second conductive wire, and the package substrate further comprises a second conductive pillar formed in the dielectric body and connecting the fourth terminal and the second conductive wire.

5. The package substrate of claim 1 , wherein the second circuit device further comprises a fourth terminal at the top of the second circuit device, and the package substrate further comprises:
a third circuit device disposed in the dielectric body, the third circuit device comprising a fifth terminal at a top of the third circuit device; and
a second bonding wire connecting the fourth terminal and the fifth terminal.

6. The package substrate of claim 1 , wherein a protective layer is formed below the dielectric body.

Assignees

• Phoenix Pioneer Technology Co Ltd
• Phoenix & Corp

Inventors

• Hu Chu-Chin
• Hsu Shih-Ping

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title