Wear leveling with wear-based attack detection for non-volatile memory

Patent metadata

Field	Value
Publication number	US-10811112-B2
Application number	US-201816147653-A
Country	US
Kind code	B2
Filing date	Sep 29, 2018
Priority date	Sep 29, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Apparatuses, systems, and methods are disclosed for wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may perform a wear-leveling process for one or more non-volatile memory elements, by periodically updating a logical-to-physical mapping and moving data based on the updated mapping. A controller may detect a wear-based attack for one or more non-volatile memory elements. A controller may change a wear-leveling process in response to detecting a wear-based attack.

First claim

What is claimed is:

1. An apparatus comprising
one or more non-volatile memory elements; and
a controller configured to:
perform a wear-leveling process for the one or more non-volatile memory elements by:
periodically updating a logical-to-physical mapping such that a number of writes between mapping updates is not divisible by the number two and the number of writes between mapping updates is not divisible by the number five, and
moving data based on the updated mapping, wherein moving the data comprises selecting, based on a data access statistic, between performing a blocking data move and performing a non-blocking data move;

detect a wear-based attack for the one or more non-volatile memory elements; and
change the wear-leveling process in response to detecting the wear-based attack.

2. The apparatus of claim 1 , wherein detecting the wear-based attack comprises determining that an access count violates a threshold, the access count comprising one or more of a read count and a write count, for a set of one or more logical addresses.

3. The apparatus of claim 1 , wherein detecting the wear-based attack comprises determining that an access count violates a threshold, the access count comprising one or more of a read count, a write count, a neighbor read count, and a neighbor write count, for a set of one or more physical addresses.

4. The apparatus of claim 1 , wherein changing the wear-leveling process comprises changing a wear-leveling parameter.

5. The apparatus of claim 1 , wherein the wear-leveling parameter comprises one or more of a trigger for updating the logical-to-physical mapping and a quantity of data to move.

6. The apparatus of claim 1 , wherein changing the wear-leveling process comprises changing a sequence of logical-to-physical mappings for updating the logical-to-physical mapping.

7. The apparatus of claim 6 , wherein changing the sequence of logical-to-physical mappings includes changing the logical to physical mapping and moving data.

8. The apparatus of claim 6 wherein changing the sequence of logical-to-physical mappings comprises changing from a first sequence to a second sequence at a mapping common to the first sequence and the second sequence.

9. The apparatus of claim 8 , wherein the controller is configured to permit access to the one or more non-volatile memory elements while changing from the first sequence to the second sequence.

10. The apparatus of claim 1 , further comprising making a further change to the wear-leveling process in response to a trigger based on one or more of a scheduled time, an age, a read count, and a write count.

11. The apparatus of claim 1 , wherein the controller is further configured to vary at least one wear-leveling parameter over time, according to one or more of a random sequence, a pseudo-random sequence, and a predetermined sequence.

12. The apparatus of claim 1 , wherein the controller is further configured to vary at least one wear-leveling parameter across elements of the one or more non-volatile memory elements.

13. The apparatus of claim 1 , wherein:
the non-blocking data move comprises waiting for data access operations to complete; and
the blocking data move comprises blocking data access operations to move the data.

14. A method comprising:
performing a wear-leveling process for one or more non-volatile memory elements by:
periodically changing a logical-to-physical mapping such that a number of writes between mapping changes is not divisible by the number two and the number of writes between mapping changes is not divisible by the number five, and
moving data based on the changed mapping, wherein moving the data comprises selecting, based on a data access statistic, between performing a blocking data move and performing a non-blocking data move;

determining whether an access count for the one or more non-volatile memory elements violates a threshold; and
modifying a wear-leveling parameter by updating a stored parameter value, in response to determining that the access count violates the threshold.

15. The method of claim 14 , further comprising varying the modified wear-leveling parameter over time, according to one or more of a random sequence, a pseudo-random sequence, and a predetermined sequence.

16. The method of claim 14 , wherein the wear-leveling parameter is modified to be coprime to the number ten.

17. The method of claim 14 , wherein updating the stored parameter value switches between sequences of logical-to-physical mappings for changing the logical-to-physical mapping.

18. An apparatus comprising:
means for wear-leveling one or more non-volatile memory elements by:
periodically updating a logical-to-physical mapping according to a set of one or more wear-leveling parameters and a sequence of logical-to-physical mappings, such that a number of writes between mapping updates is not divisible by the number two and the number of writes between mapping updates is not divisible by the number five, and
moving data based on the updated mapping, wherein moving the data comprises selecting, based on a data access statistic, between performing a blocking data move and performing a non-blocking data move;

means for detecting a wear-based attack for the one or more non-volatile memory elements; and
means for changing the sequence of logical-to-physical mappings in response to detecting the wear-based attack.

19. The apparatus of claim 18 , further comprising means for changing the set of one or more wear-leveling parameters in response to detecting the wear-based attack.

20. A system comprising:
a plurality of physical storage locations for a storage device; and
a device controller configured to:
detect a wear-based attack for the plurality of physical storage locations;
change a set of one or more wear-leveling parameters in response to detecting the wear-based attack; and
perform a wear-leveling process using the changed set of one or more wear-leveling parameters, wherein performing the wear-leveling process comprises:
periodically updating a logical-to-physical mapping such that a number of writes between mapping updates is not divisible by the number two and the number of writes between mapping updates is not divisible by the number five, and
moving data based on the updated mapping, wherein moving the data comprises selecting, based on a data access statistic, between performing a blocking data move and performing a non-blocking data move.

21. The system of claim 20 , wherein the wear-leveling process updates logical-to-physical mappings for data according to a sequence of logical-to-physical mappings, and the device controller is further configured to change the sequence in response to detecting the wear-based attack.

22. The system of claim 20 , wherein the device controller is further configured to vary at least one wear-leveling parameter across groups of physical storage locations.

23. The system of claim 20 , wherein the changed set of one or more wear-leveling parameters comprises a parameter coprime to the number ten.

24. The system of claim 20 , wherein detecting the wear-based attack comprises determining that an access count violates a threshold, the access count comprising one or more of a read count, a write count, a neighbor read count, and a neighbor write count, for one or more of a logical address, a set of logical addresses, a physical storage location, and a set of physical storage locations.

Assignees

• Western Digital Tech Inc

Inventors

• Helmick Daniel
• Gholamipour Amir
• Fitzpatrick James

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title