Non-volatile memory with dynamic wear leveling group configuration

Patent metadata

Field	Value
Publication number	US-2019108889-A1
Application number	US-201715851092-A
Country	US
Kind code	A1
Filing date	Dec 21, 2017
Priority date	Oct 11, 2017
Publication date	Apr 11, 2019
Grant date	—

Abstract

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.

First claim

What is claimed is:

1 . A non-volatile storage apparatus, comprising:
a set of non-volatile memory cells; and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.

2 . The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to split a group of physical addresses subject to a wear leveling scheme into at least a first subgroup of physical addresses and a second subgroup of physical addresses, to individually apply a first wear leveling scheme to the first subgroup of physical addresses, and to individually apply a second wear leveling scheme to the second subgroup of physical addresses.

3 . The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to merge a first group of physical addresses subject to a first wear leveling scheme and at least a second group of physical addresses subject to a second wear leveling scheme to form a merged group of physical addresses, and to apply a third wear leveling scheme to the merged group of physical addresses.

4 . The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are further configured to record one or more media properties of the set of non-volatile memory cells and to regroup physical addresses of the set of non-volatile memory cells into new wear leveling groups according to recorded media properties and to individually apply wear leveling schemes to the new wear leveling groups.

5 . The non-volatile storage apparatus of claim 4 wherein the one or more media properties include wear and wherein the one or more control circuits are configured to perform at least one of merging groups of physical addresses and splitting groups of physical addresses according to recorded wear.

6 . The non-volatile storage apparatus of claim 1 wherein the one or more control circuits include a Content Addressable Memory (CAM) configured to store meta-data.

7 . The non-volatile storage apparatus of claim 1 wherein the one or more control circuits include an Exclusive OR (XOR) circuit and the one or more control circuits are configured to apply a hypercubic wear leveling scheme to an individual group whereby logical addresses are assigned to physical addresses of the individual group by the Exclusive OR (XOR) circuit performing an Exclusive OR (XOR) operation on a logical address and a bit string to obtain a physical address.

8 . The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise Phase Change Memory (PCM) cells, Resistive Random Access Memory (ReRAM) cells, or Magnetoresistive Random Access Memory (MRAM cells).

9 . The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is formed in a plurality of memory levels disposed above a substrate in a monolithic three-dimensional memory structure.

10 . A method, comprising:
performing wear leveling operations on a set of non-volatile memory cells over a period of operation according to a wear leveling scheme; dividing the set of non-volatile memory cells into at least a first subset of the set of non-volatile memory cells and a second subset of the set of non-volatile memory cells; performing wear leveling operations on the first subset of the set of non-volatile memory cells according to a first wear leveling scheme over a subsequent period of operation; and performing wear leveling operations on the second subset of the set of non-volatile memory cells according to a second wear leveling scheme over the subsequent period of operation.

11 . The method of claim 10 wherein the dividing the set of non-volatile memory cells into at least a first subset of the set of non-volatile memory cells and a second subset of the set of non-volatile memory cells includes dividing the set of non-volatile memory cells into subsets of equal size.

12 . The method of claim 10 wherein performing wear leveling operations according to the wear leveling scheme includes performing an Exclusive OR (XOR) operation on an n-bit logical address to obtain an n-bit physical address, performing wear leveling operations on the first subset of the set of non-volatile memory cells according to the first wear leveling scheme includes performing an Exclusive OR (XOR) operation on an (n-1)-bit logical address and a first (n-1)-bit string to obtain an (n-1)-bit physical address, and performing wear leveling operations on the second subset of the set of non-volatile memory cells according to the second wear leveling scheme includes performing an Exclusive OR (XOR) operation on an (n-1)-bit logical address and a second (n-1)-bit string to obtain an (n-1)-bit physical address.

13 . The method of claim 10 wherein dividing the set of non-volatile memory cells into at least the first subset of the set of non-volatile memory cells and the second subset of the set of non-volatile memory cells is triggered by a pattern of access to memory cells of the set of non-volatile memory cells, or by a pattern of changing media characteristics.

14 . The method of claim 13 wherein the pattern of access includes frequent access directed at one or more addresses.

15 . The method of claim 10 further comprising maintaining a record of access to the set of non-volatile memory cells and searching the record of access for one or more patterns of access to the set of non-volatile memory cells, the one or more patterns of access triggering at least one of: dividing the set of non-volatile memory cells and merging the set of non-volatile memory cells with another set of non-volatile memory cells.

16 . The method of claim 10 wherein performing wear leveling operations according to the wear leveling scheme includes maintaining a gap in a logical to physical mapping and rotating the gap through physical addresses of the set of non-volatile memory cells;
performing wear leveling operations on the first subset of the set of non-volatile memory cells according to the first wear leveling scheme includes maintaining a first gap in a logical to physical mapping of the first subset of the set of non-volatile memory cells and rotating the first gap through physical addresses of the first subset of the set of non-volatile memory cells; and
performing wear leveling operations on the second subset of the set of non-volatile memory cells according to the second wear leveling scheme includes maintaining a second gap in a logical to physical mapping of the second subset of the set of non-volatile memory cells and rotating the second gap through physical addresses of the second subset of the set of non-volatile memory cells.

17 . The method of claim 10 further comprising merging the first subset of the set of non-volatile memory cells and additional non-volatile memory cells to form a merged set of non-volatile memory cells, and performing wear leveling operations on the merged set of non-volatile memory cells according to a third wear leveling scheme.

18 . The method of claim 17 further comprising:
detecting a high level of wear of the first subset of the set of non-volatile memory cells;
in response to detecting the high level of wear of the first subset of the set of non-volatile memory cells, triggering the merging of the first subset of the set of non-volatile

Assignees

• Western Digital Tech Inc

Inventors

• Gholamipour Amir
• Mishra Chandan

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C16/3495 Primary

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title