Sharing virtual and real translations in a virtual cache

Patent metadata

Field	Value
Publication number	US-10810134-B2
Application number	US-201715844239-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Jun 16, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

First claim

What is claimed is:

1. A method of operating a processor cache for a processor with virtual memory support, wherein a logically indexed and logically tagged cache directory is used, and wherein an entry in the directory contains an absolute memory address in addition to the corresponding logical memory address, and a virtual to real flag, comprising:
storing code to a logical memory address in a first entry in the cache directory;
calling, by user code, an underlying operating system;
reading, by the operating system the code from the absolute memory address;
determining if the absolute memory address is equal to the logical memory address; and
in response to determining that the absolute memory address is equal to the logical memory address, setting the virtual to real flag to on.

2. The method of claim 1 wherein the user code accesses the underlying operating system through a hypervisor.

3. The method of claim 1 wherein storing code creates a directory entry in the cache for the entry with a dynamic address translation flag set to on and a real bit flag set to off.

4. The method of claim 3 wherein when the virtual to real flag is set to on, a status of the dynamic address translation flag is ignored.

5. The method of claim 1 wherein a translation lookaside buffer is configured to return information related to the virtual to real flag.

6. The method of claim 5 wherein, for each translation lookaside buffer lookup, the virtual to real flag is recalculated.

7. A computer program product having computer executable instructions for operating a processor with virtual memory support wherein a logically indexed and logically tagged cache directory is used, and wherein an entry in the directory contains an absolute memory address in addition to a corresponding logical memory address, and a virtual to real flag, that when executed cause at least one computer to execute a method comprising:
storing code to a logical memory address in a first entry in the cache directory;
calling, by user code, an underlying operating system;
reading, by the operating system the code from the absolute memory address;
determining if the absolute memory address is equal to the logical memory address; and
in response to determining that the absolute memory address is equal to the logical memory address, setting the virtual to real flag to on.

8. The computer program product of claim 7 wherein the user code accesses the underlying operating system through a hypervisor.

9. The computer program product of claim 7 wherein storing code creates a directory entry in the cache for the entry with a dynamic address translation flag set to on and a real bit flag set to off.

10. The computer program product of claim 9 wherein when the virtual to real flag is set to on, a status of the dynamic address translation flag is ignored.

11. The computer program product of claim 7 wherein a translation lookaside buffer is configured to return information related to the virtual to real flag.

12. The computer program product of claim 11 wherein, for each translation lookaside buffer lookup, the virtual to real flag is recalculated.

Assignees

• IBM

Inventors

• Helms Markus
• Jacobi Christian
• Recktenwald Martin
• Reichart Johannes C

Classifications

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title