Debugging of prefixed code

Patent metadata

Field	Value
Publication number	US-10810104-B2
Application number	US-201916447463-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	Sep 30, 2015
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which the application code includes a prefixed instruction to be modified by a prefix, a trap is provided. The trap is configured to report a presence of the prefix, but to otherwise perform the trap functions absent the prefix; i.e., the prefix is otherwise ignored in the processing of the trap.

First claim

What is claimed is:

1. A computer program product for facilitating debugging of applications, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
providing, by one or more processors, a trap to be used in debugging of application code, the application code including a prefixed instruction, and the trap to replace the prefixed instruction by placing the trap at a selected location in the application code, wherein the selected location includes over the prefixed instruction, the trap configured to ignore the prefix in execution;
executing, by the one or more processors, the application code, wherein the executing comprises ignoring that the trap is preceded by a prefix instruction and halting the executing at the trap and transferring control to a debug control; and
based on the transferring, performing processing related debugging of the application code.

2. The computer program product of claim 1 , wherein the prefix is provided via a prefix instruction placed in the application code prior to the prefixed instruction.

3. The computer program product of claim 2 , wherein the prefix instruction and the prefixed instruction are individual instructions initially provided separately to decode units to be decoded.

4. The computer program product of claim 1 , the method further comprising:
restarting, by the one or more processors, execution of the application code at the prefixed instruction.

5. The computer program product of claim 4 , wherein the restarting comprises:
replacing, by the one or more processors, the trap with the prefixed instruction; and
resuming execution of the application code at the prefixed instruction.

6. The computer program product of claim 4 , wherein the method further comprises using another trap to debug the application code, the other trap to be placed at a chosen location within the application code, the chosen location being one of over the prefix instruction or over another prefixed instruction.

7. The computer program product of claim 1 , wherein executing the application code further comprises:
reporting the presence of the prefix.

8. The computer program product of claim 7 , wherein the reporting the presence of the prefix includes reporting at least one of an address of the prefix instruction or an indication of the prefix instruction.

9. The computer program product of claim 7 , wherein the reporting the presence of the prefix includes reporting an address of the trap and an indication that the trap was taken.

10. The computer program product of claim 8 , wherein the reporting further comprises reporting a length of the prefix.

11. The computer program product of 1 , wherein the prefixed instruction is defined to be modified by a prefix.

12. The computer program product of 1 , wherein the trap is further configured to report a presence of the prefix.

13. A computer system for facilitating debugging of applications, the computer system comprising:
a memory; and
one or more processors in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
providing, by the one or more processors, a trap to be used in debugging of application code, the application code including a prefixed instruction, and the trap to replace the prefixed instruction by placing the trap at a selected location in the application code, wherein the selected location includes over the prefixed instruction, the trap configured to ignore the prefix in execution;
executing, by the one or more processors, the application code, wherein the executing comprises ignoring that the trap is preceded by a prefix instruction and halting the executing at the trap and transferring control to a debug control; and
based on the transferring, performing processing related debugging of the application code.

14. The computer system of claim 13 , wherein the prefix is provided via a prefix instruction placed in the application code prior to the prefixed instruction.

15. The computer system of claim 14 , wherein the prefix instruction and the prefixed instruction are individual instructions initially provided separately to decode units to be decoded.

16. The computer system of claim 13 , the method further comprising:
restarting, by the one or more processors, execution of the application code at the prefixed instruction.

17. The computer system of claim 16 , wherein the restarting comprises:
replacing, by the one or more processors, the trap with the prefixed instruction; and
resuming execution of the application code at the prefixed instruction.

18. The computer system of claim 16 , wherein the method further comprises using another trap to debug the application code, the other trap to be placed at a chosen location within the application code, the chosen location being one of over the prefix instruction or over another prefixed instruction.

19. The computer system of claim 13 , wherein the prefixed instruction is defined to be modified by a prefix.

20. The computer system of claim 13 , wherein the trap is further configured to report a presence of the prefix.

Assignees

• IBM

Inventors

• Gschwind Michael K

Classifications

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/355

  Indexed addressing · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/324

  using program counter relative addressing · CPC title