Prefix computer instruction for compatibily extending instruction functionality

Patent metadata

Field	Value
Publication number	US-9329869-B2
Application number	US-201113251426-A
Country	US
Kind code	B2
Filing date	Oct 3, 2011
Priority date	Oct 3, 2011
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.

First claim

What is claimed is:

1. A computer implemented method for executing instructions, the method comprising:
obtaining a first instruction and a second instruction for execution, the first instruction preceding the second instruction in program order;
determining, by a processor, that the first instruction is a prefix instruction, the prefix instruction specifying a first value to be used as a result operand in executing the first instruction and a location for storing the result operand, the second instruction specifying a value to be used as a source operand in executing the second instruction and a location for fetching the source operand, wherein the result operand of the first instruction is the source operand of the second instruction;
executing the first instruction without storing the result operand at the location specified by the first instruction; and
executing the second instruction using the first value without fetching the source operand from the location specified by the second instruction.

2. The method according to claim 1 , the determining further comprising determining that there is no intervening interruption event between the execution of the first instruction and the second instruction.

3. The method according to claim 2 , wherein the first value to be used in executing the second instruction is identified as a result register of the first instruction, wherein the result, register of the first instruction is a source register of the second instruction.

4. The method according to claim 3 , wherein the result register is an architected register associated with an architected instruction set, consisting of any one of a general register or a floating point register.

5. The method according to claim 2 , wherein the locations specified by the first and second instructions are main storage locations.

6. The method according to claim 1 , wherein the first value to be used comprises a result of executing the first instruction and an immediate field of the first instruction, the executing the second instruction further comprising using a concatenated value of at least part of the immediate field of the first instruction and an immediate field of the second instruction.

7. The method according to claim 1 , further comprising:
forming a single internal instruction based on the first instruction and second instruction, wherein the executing comprises executing the single internal instruction.

Assignees

• Gschwind Michael K
• Salapura Valentina
• IBM

Inventors

• Gschwind Michael K
• Salapura Valentina

Classifications

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/30185 Primary

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title