Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element

Patent metadata

Field	Value
Publication number	US-10805437-B2
Application number	US-201916383276-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Jul 9, 2017
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

A method of configuring a forwarding element that includes several data plane message processing stages. The method stores a set of action codes in an instruction memory in the data plane of the forwarding element. Each action code identifies an operation to perform on a field of a message received at the data plane. The method determines action codes required to process each field of the message in each message processing stage. The method configures a data-plane processing unit of the forwarding element to concurrently perform a group of the action codes in the same data plane processing stage when (i) the action codes are the same and (ii) operate on the same field of the message.

First claim

What is claimed is:

1. A method for determining a configuration for a data plane message processing pipeline of a hardware forwarding element comprising a plurality of message processing stages, the method comprising:
identifying a set of message processing instructions for the data plane message processing pipeline to execute on data messages received by the hardware forwarding element, the set of message processing instructions comprising action codes to be stored in instruction memories of the message processing stages, the action codes specifying actions for the message processing stages to perform on data message fields of the data messages;
determining that the set of message processing instructions specifies that a plurality of action codes for a particular data message field are to be stored in the instruction memory of a particular message processing stage; and
when the plurality of action codes specify different actions for the particular message processing stage to perform on the particular data message field, specifying that a subset of the plurality of the action codes are to be stored in the instruction memories of different message processing stages.

2. The method of claim 1 , wherein the particular data message field is a first data message field and the plurality of action codes is a first plurality of action codes, the method further comprising:
determining that the set of message processing instructions specifies that a second plurality of action codes for a second data message field are to be stored in the instruction memory of the particular message processing stage; and
when the second plurality of action codes all specify the same action for the particular message processing stage to perform on the second data message field, allowing the second plurality of action codes to be stored in the instruction memories of the particular message processing stage.

3. The method of claim 1 , wherein the particular message processing stage comprises circuitry to perform a logical OR operation on action codes read from the instruction memory of the particular message processing stage for the particular data message field.

4. The method of claim 3 , wherein for a particular data message, a plurality of sets of action codes are read from the instruction memories of the particular message processing stage, wherein each set of action codes comprises action codes for each of a set of data message header fields.

5. The method of claim 1 , wherein the particular message processing stage comprises a set of data plane processing circuits that execute the action codes stored in the instruction memories of the particular message processing stage.

6. The method of claim 5 , wherein each of the data plane processing circuits is configured to execute action codes for a different data message field.

7. The method of claim 5 , wherein the data plane processing circuits are arithmetic logic units (ALUs).

8. The method of claim 1 , wherein the set of instructions is specified in a data plane programming language.

9. The method of claim 8 , wherein the data plane programming language is P4.

10. The method of claim 1 , wherein the particular message processing stage is a first message processing stage and the plurality of action codes is a first plurality of action codes, the method further comprising:
determining that the set of message processing instructions specifies that a second plurality of action codes for the particular data message field are to be stored in the instruction memory of a second message processing stage; and
when the second plurality of action codes all specify the same action for the second message processing stage to perform on the particular data message field, allowing the second plurality of action codes to be stored in the instruction memories of the second message processing stage.

11. The method of claim 1 , wherein the particular message processing stage is a first message processing stage and the plurality of action codes is a first plurality of action codes, the method further comprising:
determining that the set of message processing instructions specifies that a second plurality of action codes for the particular data message field are to be stored in the instruction memory of a second message processing stage; and
when the second plurality of action codes specify different actions for the second message processing stage to perform on the particular data message field, specifying that a subset of the second plurality of action codes are to be stored in the instruction memories of different message processing stages.

12. The method of claim 1 , wherein data messages received by the hardware forwarding element are processed by the plurality of message processing stages of the data plane message processing pipeline.

13. The method of claim 1 , wherein the data plane message processing pipeline further comprises a parser and a deparser.

14. The method of claim 13 , wherein the parser receives a data message and parses the data message to store data message header field values in data containers of a packet header vector that are passed to the message processing stages.

15. The method of claim 14 , wherein the message processing stages perform actions on data message fields of the data messages by modifying values stored in the data containers of the packet header vector.

16. The method of claim 14 , wherein the deparser receives the packet header vector modified by the message processing stages and reconstitutes a modified data message.

17. The method of claim 1 further comprising determining whether the set of message processing instructions specifies that a plurality of different action codes for the particular data message field are to be stored in the instruction memory for each of the message processing stages.

18. The method of claim 1 further comprising determining whether the set of message processing instructions specifies that a plurality of different action codes for each of a plurality of different data message fields are to be stored in the instruction memory for the particular message processing stage.

19. The method of claim 1 further comprising determining whether the set of message processing instructions specifies that a plurality of different action codes for each of a plurality of different data message fields are to be stored in the instruction memory for each of the message processing stages.

Assignees

• Barefoot Networks Inc

Inventors

• Bosshart Patrick
• Ferrara Michael Gregory
• Attig Michael E
• Peterson Jay Evan Scott

Classifications

• H04L69/22 Primary

  Parsing or analysis of headers · CPC title

• H04L45/74

  Address processing for routing · CPC title

• H04L45/745

  Address table lookup; Address filtering · CPC title

• H04L41/0803

  Configuration setting · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title