Configuring a switch for extracting packet header fields

Patent metadata

Field	Value
Publication number	US-9826071-B2
Application number	US-201514836855-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Aug 26, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A method for generating configuration data for configuring a hardware switch is described. The method receives a description of functionality for the hardware switch. Based on the description, the method generates sets of match and action entries to configure the hardware switch to process packets. The method then determines, for each packet header field in a parse graph that specifies instructions for a parser of the switch to extract packet header fields from packets, whether the packet header field is used or modified by at least one match or action entry. The method generates for the parser of the hardware switch configuration data that instructs the parser to extract (i) packet header fields used or modified by at least one match or action entry to a first set of registers and (ii) packet header fields not used by any match or action entries to a second set of registers.

First claim

What is claimed is:

1. A method for generating configuration data for configuring a hardware switch, the method comprising:
receiving a description of functionality for the hardware switch;
based on the description, generating sets of match and action entries for use in configuring the hardware switch to process packets through a plurality of stages that match against packet header fields and modify packet header fields;
determining, for each packet header field in a parse graph that specifies instructions for a parser of the switch to extract packet header fields from packets, whether the packet header field is used by at least one match entry or modified by at least one action entry; and
generating configuration data for the parser of the hardware switch, wherein the configuration data instructs the parser (i) to extract packet header fields used by at least one match entry or modified by at least one action entry to a first set of registers and (ii) to extract packet header fields not used by any match or action entries to a second set of registers.

2. The method of claim 1 , wherein the description of functionality for the hardware switch comprises program code describing the switch functionality.

3. The method of claim 2 , wherein the program code is written in P4 switch description language.

4. The method of claim 1 , wherein generating sets of match and action entries comprises generating a table flow graph that specifies the match and action entries of match and action tables to be implemented by the switch.

5. The method of claim 1 , wherein the parse graph comprises a plurality of nodes each of which represents a packet header and a plurality of directed edges connecting the nodes.

6. The method of claim 5 , wherein an edge from a first node to a second node specifies that a particular header field value of the packet header represented by the first node identifies a next packet header represented by the second node.

7. The method of claim 5 , wherein each node in the parse graph specifies a format of the packet header fields of the packet header represented by the node.

8. The method of claim 5 , wherein each edge of the parse graph is represented in the configuration data by a match entry.

9. The method of claim 8 , wherein each match entry is implemented in a TCAM in the parser of the hardware switch.

10. The method of claim 1 , wherein the first set of registers is sent to a match-action unit (MAU) of the hardware switch that implements the plurality of stages, while the second set of registers is sent directly to a deparser of the hardware switch without being processed by the MAU of the hardware switch.

11. The method of claim 10 further comprising generating configuration data for the MAU of the hardware switch.

12. The method of claim 10 , wherein each stage of the MAU comprises a set of match tables against which values of at least a subset of the packet header fields stored in the first set of registers are matched.

13. The method of claim 12 , wherein each of the MAU stages further comprises a set of action entries and an action engine for performing a set of actions specified by an action entry that corresponds to a match entry of the set of match tables of the stage that is matched by the subset of packet header field values.

14. A non-transitory machine readable medium storing a program executable by one or more processing units, the program for generating configuration data that configures a hardware switch, the program comprising sets of instructions for:
receiving a description of functionality for the hardware switch;
based on the description, generating sets of match and action entries for use in configuring the hardware switch to process packets through a plurality of stages that match against packet header fields and modify packet header fields;
determining, for each packet header field in a parse graph that specifies instructions for a parser of the switch to extract packet header fields from packets, whether the packet header field is used by at least one match entry or modified by at least one action entry; and
generating configuration data for the parser of the hardware switch, wherein the configuration data instructs the parser (i) to extract packet header fields used by at least one match entry or modified by at least one action entry to a first set of registers and (ii) to extract packet header fields not used or modified by any match or action entries to a second set of registers.

15. The machine readable medium of claim 14 , wherein the description of functionality for the hardware switch comprises program codes that describe the switch functionality.

16. The machine readable medium of claim 15 , wherein the program codes are written in P4 switch description language.

17. The machine readable medium of claim 14 , wherein the set of instructions for generating sets of match and action entries comprises a set of instructions for generating a table flow graph that specifies the match and action entries of match and action tables to be implemented by the switch.

18. The machine readable medium of claim 14 , wherein the parse graph comprises a plurality of nodes each of which represents a packet header and a plurality of directed edges connecting the nodes.

19. The machine readable medium of claim 18 , wherein an edge from a first node to a second node specifies that a particular header field value of the packet header represented by the first node identifies a next packet header represented by the second node.

20. The machine readable medium of claim 19 , wherein each node in the parse graph specifies a format of the packet header fields of the packet header represented by the node and each edge of the parse graph is represented in the configuration data by a match entry.

Assignees

• Barefoot Networks Inc

Inventors

• Bosshart Patrick

Classifications

• H04L69/22 Primary

  Parsing or analysis of headers · CPC title

• H04L49/3009

  Header conversion, routing tables or routing tags · CPC title

• H04L45/745

  Address table lookup; Address filtering · CPC title