Packet header field extraction

US9825862B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9825862-B2
Application numberUS-201514836850-A
CountryUS
Kind codeB2
Filing dateAug 26, 2015
Priority dateAug 26, 2015
Publication dateNov 21, 2017
Grant dateNov 21, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for processing a packet for a pipeline of a hardware switch, the pipeline comprising a plurality of stages that match against packet header fields and modify packet header fields, the method comprising: receiving a packet comprising a set of packet headers; for each packet header in the set of packet headers: populating a first set of registers with packet header field values of the packet header that are used in the pipeline; and populating a second set of registers with packet header field values of the packet header that are not used in the pipeline. 2. The method of claim 1 , wherein the pipeline comprises one of an ingress pipeline and an egress pipeline of the hardware switch. 3. The method of claim 1 , wherein the pipeline comprises a parser, a match-action unit (MAU), and a deparser, wherein the first set of registers is delivered to the MAU for further processing and the second set of registers is delivered directly to the deparser without being processed by the MAU. 4. The method of claim 3 , wherein the MAU comprises a set of match-action stages, each of which comprises a set of match tables against which at least a subset of the packet header field values stored in the first set of registers is matched. 5. The method of claim 4 , wherein each of the match-action stages of the MAU further comprises a set of action entries and an action engine for performing a set of actions specified by an action entry that corresponds to a match entry of the set of match tables of the match-action stage. 6. The method of claim 5 , wherein the set of actions comprises modifying one or more of the header field values stored in the first set of registers. 7. The method of claim 1 , wherein for a particular packet, only a first subset of the packet header field values stored in the first set of registers are used in the pipeline. 8. The method of claim 7 , wherein a second subset of the packet header field values stored in the first set of registers are not used for the particular packet, but used for other packets. 9. The method of claim 7 , wherein a particular packet header field value is used in the pipeline when either (i) a match entry matches against the packet header field value or (ii) an action entry modifies the packet header field value. 10. The method of claim 1 , wherein the first set of registers are populated with values of different packet header fields for a first packet than for a second packet based on the values of a particular packet header field in the packet headers of the first and second packets. 11. The method of claim 10 , wherein the particular packet header field is the EtherType field of Ethernet headers. 12. The method of claim 1 further comprising, for each of at least a subset of the packet headers, determining a format of a next packet header by matching a value of a particular packet header field of the packet header against a set of TCAM entries. 13. A non-transitory machine readable medium storing a program which when executed by at least one processing unit processes a packet for a pipeline of a hardware switch, the pipeline comprising a plurality of stages that match against packet header fields and modify packet header fields, the program comprising sets of instructions for: receiving a packet comprising a set of packet headers; for each packet header in the set of packet headers: populating a first set of registers with packet header field values of the packet header that are used in the pipeline; and populating a second set of registers with packet header field values of the packet header that are not used in the pipeline. 14. The machine readable medium of claim 13 , wherein the pipeline comprises one of an ingress pipeline and an egress pipeline of the hardware switch. 15. The machine readable medium of claim 13 , wherein the pipeline comprises a parser, a match-action unit (MAU), and a deparser, wherein the program further comprises sets of instructions for: delivering the first set of registers to the MAU for further processing; and delivering the second set of registers directly to the deparser without having the MAU process the second set. 16. The machine readable medium of claim 15 , wherein the MAU comprises a set of match-action stages, each of which comprises a set of match tables against which at least a subset of the packet header field values stored in the first set of registers is matched. 17. The machine readable medium of claim 16 , wherein each of the match-action stages of the MAU further comprises a set of action entries and an action engine for performing a set of actions specified by an action entry that corresponds to a match entry of the set of match tables of the match-action stage. 18. The machine readable medium of claim 17 , wherein the set of actions comprises modifying one or more of the header field values stored in the first set of registers. 19. The machine readable medium of claim 13 , wherein for a particular packet, only a first subset of the packet header field values stored in the first set of registers are used in the pipeline. 20. The machine readable medium of claim 13 , wherein the program further comprises, for each of at least a subset of the packet headers, determining a format of a next packet header by matching a value of a particular packet header field of the packet header against a set of TCAM entries.

Assignees

Inventors

Classifications

  • Organization of routing tables · CPC title

  • Parsing or analysis of headers · CPC title

  • H04L45/64Primary

    using an overlay routing layer · CPC title

  • using crossbar or matrix · CPC title

  • Centralised routing · CPC title

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Frequently asked questions

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What does patent US9825862B2 cover?
Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first …
Who is the assignee on this patent?
Barefoot Networks Inc
What technology area does this patent fall under?
Primary CPC classification H04L45/64. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).