Indirect readout FET

Patent metadata

Field	Value
Publication number	US-10804261-B2
Application number	US-201916662284-A
Country	US
Kind code	B2
Filing date	Oct 24, 2019
Priority date	May 3, 2017
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

First claim

What is claimed is:

1. A metal-insulator-metal (MIM) capacitor structure comprising:
a dielectric layer formed over a first conducting layer;
a second conducting layer formed over the dielectric layer; and
a sidewall dielectric formed adjacent the first conducting layer;
wherein an electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel.

2. The structure of claim 1 , wherein source and drain regions are formed within a semiconductor substrate.

3. The structure of claim 2 , wherein the first conducting layer is formed over the source and drain regions.

4. The structure of claim 3 , wherein the sidewall dielectric is further formed adjacent the dielectric layer.

5. The structure of claim 4 , wherein pinning layers are formed on opposed ends of the dielectric layer.

6. The structure of claim 5 , wherein the pinning layers have opposite polarization relative to each other resulting in the dielectric layer separated into two regions by a domain boundary, the two regions having opposite polarization relative to each other.

7. The structure of claim 6 , wherein the domain boundary shifts based on a voltage applied to the MIM capacitor structure.

8. The structure of claim 7 , wherein the sidewall dielectric is traverse to the FET to divide the FET channel longitudinally into two regions of varying lengths and different resistivities.

9. The structure of claim 7 , wherein the sidewall dielectric extends along the FET channel to divide a width of the FET channel into two regions.

10. The structure of claim 1 , wherein the sidewall dielectric defines a high permittivity spacer.

11. The structure of claim 1 , wherein the first conducting layer is a titanium nitride (TiN) layer and the dielectric layer is a ferroelectric layer.

12. The structure of claim 1 , wherein the sidewall dielectric is hafnium oxide.

13. The structure of claim 1 , wherein a doped region is formed under and in direct contact with the sidewall dielectric.

14. A metal-insulator-metal (MIM) capacitor structure comprising:
a sidewall dielectric disposed adjacent a first conducting layer and a dielectric layer;
wherein an electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel.

15. The structure of claim 14 , wherein:
the dielectric layer is disposed over the first conducting layer; and
a second conducting layer is disposed over the dielectric layer.

16. The structure of claim 15 , wherein source and drain regions are disposed within the semiconductor substrate.

17. The structure of claim 16 , wherein the first conducting layer is disposed over the source and drain regions.

18. The structure of claim 14 , wherein pinning layers are formed on opposed ends of the dielectric layer.

19. The structure of claim 18 , wherein the pinning layers have opposite polarization relative to each other resulting in the dielectric layer separated into two regions by a domain boundary, the two regions having opposite polarization relative to each other.

20. The structure of claim 19 , wherein
the domain boundary shifts based on a voltage applied to the MIM capacitor structure; and
wherein the sidewall dielectric is traverse to the FET to divide the FET channel longitudinally into two regions of varying lengths and different resistivities.

Assignees

• IBM

Inventors

• Han Jin-Ping
• Li Yulong
• Newns Dennis M
• Solomon Paul M
• Sun Xiao

Classifications

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title