Indirect readout FET

Patent metadata

Field	Value
Publication number	US-10332874-B2
Application number	US-201715585876-A
Country	US
Kind code	B2
Filing date	May 3, 2017
Priority date	May 3, 2017
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

First claim

What is claimed is:

1. A metal-insulator-metal (MIM) capacitor structure comprising:
source and drain regions formed within a semiconductor substrate;
a first conducting layer formed over the source and drain regions;
a dielectric layer formed over the first conducting layer;
a second conducting layer formed over the dielectric layer; and
a slot defined in the first conducting layer;
wherein the slot allows modulation of a field effect transistor (FET) channel formed in the semiconductor substrate.

2. The structure of claim 1 , wherein the first conducting layer is a titanium nitride (TiN) layer.

3. The structure of claim 1 , wherein the dielectric layer is a ferroelectric layer.

4. The structure of claim 1 , wherein pinning layers are formed on opposed ends of the slot.

5. The structure of claim 1 , wherein a width of the slot is less than a total width of the dielectric layer.

6. The structure of claim 1 , wherein the second conducting layer is a gate electrode.

7. A metal-insulator-metal (MIM) capacitor structure comprising:
source and drain regions formed within a semiconductor substrate;
a first conducting layer formed over the source and drain regions;
a doped region defined between the source and drain regions;
a dielectric layer formed over the first conducting layer;
a second conducting layer formed over the dielectric layer; and
a slot defined in the first conducting layer, the slot being aligned with the doped region;
wherein the slot allows modulation of a field effect transistor (FET) channel formed in the semiconductor substrate.

8. The structure of claim 7 , wherein pinning layers are formed on opposed ends of the dielectric layer.

9. The structure of claim 8 , wherein the pinning layers have opposite polarization relative to each other resulting in the dielectric layer separated into two regions by a domain boundary, the two regions having opposite polarization relative to each other.

10. The structure of claim 9 , wherein the domain boundary shifts based on a voltage applied to the MIM capacitor structure.

11. The structure of claim 10 , wherein the sidewall dielectric is traverse to the FET to divide the FET channel longitudinally into two regions of varying lengths and different resistivities.

12. The structure of claim 10 , wherein the sidewall dielectric extends along the FET channel to divide a width of the FET channel into two regions.

Assignees

• IBM

Inventors

• Han Jin-Ping
• Li Yulong
• Newns Dennis M
• Solomon Paul M
• Sun Xiao

Classifications

• H01L27/0629 Primary

  Electricity · mapped topic

• H01L29/516

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H10D64/689

  having ferroelectric layers · CPC title