Microelectronics package with vertically stacked dies

Patent metadata

Field	Value
Publication number	US-10804246-B2
Application number	US-201816004961-A
Country	US
Kind code	B2
Filing date	Jun 11, 2018
Priority date	Jun 11, 2018
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

First claim

What is claimed is:

1. An apparatus comprising:
a module board;
a first thinned flip-chip die comprising a first device layer, a first through-die via, and a first package contact, wherein:
a top portion of the first through-die via is exposed at a top of the first thinned flip-chip die;
the first package contact is exposed at a bottom of the first thinned flip-chip die, and is coupled to the module board; and
the first device layer includes a first device component, which is electrically coupled to the first through-die via and the first package contact;

a first mold compound residing over the module board, underfilling the first thinned flip-chip die, encapsulating sides of the first thinned flip-chip die, and extending vertically beyond the first thinned flip-chip die to define a first opening within the first mold compound and vertically above the first thinned flip chip die, wherein the first mold compound does not reside over the first thinned flip chip die; and
a second flip-chip die stacked with the first thinned flip chip die, residing within the first opening, and over the first thinned flip chip die, wherein:
the second flip-chip die has a smaller plane size than the first thinned flip-chip die;
the second flip-chip die comprises a second device layer and a second package contact, which is exposed at a bottom of the second flip-chip die, and is coupled to the first through-die via; and
the second device layer includes a second device component, which is electrically coupled to the second package contact.

2. The apparatus of claim 1 wherein the first thinned flip-chip die does not include a silicon handle layer and further includes a first stop layer, a first back-end-of-line (BEOL) layer, and a first redistribution structure with the first package contact, wherein:
the first stop layer resides over the first device layer and is exposed at the top of the first thinned flip-chip die;
the first BEOL layer resides underneath the first device layer;
the first redistribution structure resides underneath the first BEOL layer and at the bottom of the first thinned flip-chip die; and
the first through-die via extends through the first BEOL layer, the first device layer, and the first stop layer, wherein the top portion of the first through-die via extends beyond the first stop layer.

3. The apparatus of claim 1 wherein the exposed top portion of the first through-die via has a thickness between 0 and 100 μm.

4. The apparatus of claim 1 wherein the first through-die via is formed of one of a group consisting of platinum, gold, silver, copper, aluminum, tungsten, titanium, and electrically conductive epoxy.

5. The apparatus of claim 1 wherein the second flip-chip die further comprises a second stop layer, a silicon handle layer, a second BEOL layer, and a second redistribution structure with the second package contact, wherein:
the second stop layer resides over the second device layer;
the silicon handle layer resides over the second stop layer and at the top of the second flip-chip die;
the second BEOL layer resides underneath the second device layer; and
the second redistribution structure resides underneath the second BEOL layer and at the bottom of the second flip-chip die.

6. The apparatus of claim 5 further comprises a second mold compound filling the first opening, wherein:
the second mold compound resides over the first thinned flip-chip die, such that the second mold compound encapsulates the second package contact and the exposed top portion of the first through-die via, and underfills the second flip-chip die between the second redistribution structure and the first thinned flip-chip die;
the second mold compound is directly surrounded by the first mold compound; and
the second mold compound fully encapsulates the second flip-chip die.

7. The apparatus of claim 6 wherein the first mold compound and the second mold compound are formed from a same material.

8. The apparatus of claim 6 wherein the first mold compound and the second mold compound have a thermal conductivity greater than 1 W/m·K, and have an electrical resistivity greater than 1E6 Ohm-cm.

9. The apparatus of claim 1 wherein the second flip-chip die is a thinned flip-chip die that does not comprise a silicon handle layer and further comprises a second stop layer, a second BEOL layer, and a second redistribution structure with the second package contact, wherein:
the second stop layer resides over the second device layer and is exposed at a top of the second flip-chip die;
the second BEOL layer resides underneath the second device layer; and
the second redistribution structure resides underneath the second BEOL layer and at the bottom of the second flip-chip die.

10. The apparatus of claim 9 further comprises a second mold compound, wherein:
the second mold compound resides over the first thinned flip-chip die, such that the second mold compound encapsulates the second package contact and the exposed top portion of the first through-die via, and underfills the second flip-chip die between the second redistribution structure and the first thinned flip-chip die;
the second mold compound is directly surrounded by the first mold compound; and
the second mold compound encapsulates sides of the second flip-chip die, and extends vertically beyond the second flip-chip die to define a second opening within the second mold compound and vertically above the second flip chip die, wherein the second mold compound does not reside over the second flip chip die.

11. The apparatus of claim 10 further comprises a third mold compound, which resides over the second flip-chip die, fills the second opening, and is directly surrounded by the second mold compound.

12. The apparatus of claim 11 wherein the first mold compound, the second mold compound, and the third mold compound are formed from a same material.

13. The apparatus of claim 9 wherein the second flip-chip die further comprises a second through-die via that extends through the second BEOL layer, the second device layer, and the second stop layer, wherein a top portion of the second through-die via extends beyond the second stop layer and is exposed at the top of the second flip-chip die.

14. The apparatus of claim 13 further comprises a second mold compound, wherein:
the second mold compound resides over the first thinned flip-chip die, such that the second mold compound encapsulates the second package contact and the exposed top portion of the first through-die via, and underfills the second flip-chip die between the second redistribution structure and the first thinned flip-chip die;
the second mold compound is directly surrounded by the first mold compound; and
the second mold compound encapsulates sides of the second flip-chip die, and extends vertically beyond the second flip-chip die to define a second opening within the second mold compound and vertically above the second flip chip die, wherein the second mold compound does not reside over the second flip chip die.

15. The apparatus of claim 14 further comprises a third flip-chip die stacked with the second flip chip die, residing within the second opening, and over the second flip chip die, wherein:
the third flip-chip die has a smaller plane size than the second flip-chip die;
the third flip-chip die comprises a third device layer and a third package contact, which is exposed at a bottom of the third flip-chip die, and is coupled to the second through-die via; and
the third device layer includes a third device component, which is electrically coupled to the third package contact.

Assignees

• Qorvo Us Inc

Inventors

• Costa Julio C
• Aigner Robert
• Fattinger Gernot
• Leipold Dirk Robert Walter
• Maxim George
• Scott Baker
• Hatcher Jr Merrill Albert
• Chadwick Jon

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title