Hybrid analog-digital matrix processors

Patent metadata

Field	Value
Publication number	US-10803258-B2
Application number	US-202016800998-A
Country	US
Kind code	B2
Filing date	Feb 25, 2020
Priority date	Feb 26, 2019
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

First claim

What is claimed is:

1. A hybrid analog-digital processor comprising:
circuitry comprising an analog processor, wherein the circuitry is configured to perform a mathematical operation using a plurality of passes, wherein for each of the plurality of passes, the circuitry is configured to:
determine one or more scaling factors for the pass based on a set of parameters representing a portion of a matrix;
scale at least some parameters of the set of parameters based on the one or more scaling factors to produce a scaled set of parameters;
program the analog processor based on the scaled set of parameters;
generate a plurality of input analog signals based on an input data set;
generate a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters;
generate a partial output data set based on the plurality of output analog signals; and
scale the partial output data set based on the one or more scaling factors to produce a scaled partial output data set,

wherein the circuitry is further configured to generate an accumulated output data set by accumulating the scaled partial output data sets generated by at least two of the plurality of passes, wherein the accumulated output data set represents a result of the mathematical operation.

2. The hybrid analog-digital processor of claim 1 , wherein generating a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters comprises performing a matrix-matrix multiplication based on the plurality of input analog signals and the scaled set of parameters.

3. The hybrid analog-digital processor of claim 1 , wherein generating a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters comprises performing a convolution based on the plurality of input analog signals and the scaled set of parameters.

4. The hybrid analog-digital processor of claim 1 , wherein the analog processor comprises a photonic processor comprising a plurality of programmable photonic devices, and wherein programming the analog processor based on the scaled set of parameters comprises setting respective characteristics for the plurality of programmable photonic devices based on the scaled set of parameters.

5. The hybrid analog-digital processor of claim 4 , wherein the programmable photonic devices comprise Mach-Zehnder interferometers, and wherein setting respective characteristics for the plurality of programmable photonic devices based on the scaled set of parameters comprises:
setting respective optical characteristics for the plurality of Mach-Zehnder interferometers based on the scaled set of parameters.

6. The hybrid analog-digital processor of claim 4 , wherein the programmable photonic devices comprise optical resonators, and wherein setting respective characteristics for the plurality of programmable photonic devices based on the scaled set of parameters comprises:
setting respective optical characteristics for the plurality of optical resonators based on the scaled set of parameters.

7. The hybrid analog-digital processor of claim 1 , wherein programming the analog processor comprises:
programming, based on the scaled set of parameters, the analog processor with a plurality of matrices that, collectively, represent an arbitrary matrix.

8. The hybrid analog-digital processor of claim 7 , wherein programming the analog processor with a plurality of matrices comprises:
programming, based on the scaled set of parameters, the analog processor with a plurality of matrices that, collectively, represent the arbitrary matrix based on a singular value decomposition (SVD) of the arbitrary matrix.

9. The hybrid analog-digital processor of claim 1 , wherein, for each of the plurality of passes, the circuitry is further configured to determine the one or more scaling factors based on a tile of the matrix that is associated with the pass.

10. A method for performing a mathematical operation using a plurality of passes through an analog processor, the method comprising:
for each of the plurality of passes:
determining one or more scaling factors for the pass based on a set of parameters representing a portion of a matrix;
scaling at least some parameters of the set of parameters based on the one or more scaling factors to produce a scaled set of parameters;
programming the analog processor based on the scaled set of parameters;
generating a plurality of input analog signals based on an input data set;
generating a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters;
generating a partial output data set based on the plurality of output analog signals; and
scaling the partial output data set based on the one or more scaling factors to produce a scaled partial output data set; and

generating an accumulated output data set by accumulating the scaled partial output data sets generated by at least two of the plurality of passes, wherein the accumulated output data set represents a result of the mathematical operation.

11. The method of claim 10 , wherein generating a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters comprises performing a matrix-matrix multiplication based on the plurality of input analog signals and the scaled set of parameters.

12. The method of claim 10 , wherein generating a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters comprises performing a convolution based on the plurality of input analog signals and the scaled set of parameters.

13. The method of claim 10 , wherein the analog processor comprises a photonic processor comprising a plurality of programmable photonic devices, and wherein programming the analog processor based on the scaled set of parameters comprises setting respective characteristics for the plurality of programmable photonic devices based on the scaled set of parameters.

14. The method of claim 13 , wherein the programmable photonic devices comprise Mach-Zehnder interferometers, and wherein setting respective characteristics for the plurality of programmable photonic devices based on the scaled set of parameters comprises:
setting respective optical characteristics for the plurality of Mach-Zehnder interferometers based on the scaled set of parameters.

15. The method of claim 13 , wherein the programmable photonic devices comprise optical resonators, and wherein setting respective characteristics for the plurality of programmable photonic devices based on the scaled set of parameters comprises:
setting respective optical characteristics for the plurality of optical resonators based on the scaled set of parameters.

16. The method of claim 10 , wherein programming the analog processor comprises:
programming, based on the scaled set of parameters, the analog processor with a plurality of matrices that, collectively, represent an arbitrary matrix.

17. The method of claim 16 , wherein programming the analog processor with a plurality of matrices comprises:
programming, based on the scaled set of parameters, the analog processor with a plurality of matrices that, collectively, represent the arbitrary matrix based on a singular value decomposition (SVD) of the arbitrary matrix.

18. The method of claim 10 , wherein determining the one or more scaling factors comprises determining the one or more scaling factors based on a tile of the matrix t

Assignees

• Lightmatter Inc

Inventors

• Kenney Tyler J
• Forsythe Martin B Z
• Lazovich Tomo
• Bunandar Darius

Classifications

• G06N3/065

  Analogue means · CPC title

• G06J1/02 Primary

  Differential analysers · CPC title

• G06J1/005 Primary

  for correlation; for convolution; for Z or Fourier Transform · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F7/523

  Multiplying only · CPC title