Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016118106-A1
Application number	US-201314890335-A
Country	US
Kind code	A1
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	Apr 28, 2016
Grant date	—

Abstract

It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

First claim

1 .- 14 . (canceled)

15 . A semiconductor device comprising:
a first memory cell; and a second memory cell that interacts with the first memory cell, wherein storage content of the first memory cell and the second memory cell is stochastically inverted.

16 . The semiconductor device according to claim 15 ,
wherein the storage content is stochastically inverted by changing threshold voltages of the first memory cell and the second memory cell.

17 . The semiconductor device according to claim 16 , further comprising,
first and second registers, wherein a control voltage for controlling the threshold voltages of the first memory cell and the second memory cell is changed with passage of time, and when the control voltage reaches a condition designated by the first register, the control voltage is set to a voltage based on a value designated by the second register.

18 . The semiconductor device according to claim 17 ,
wherein the control voltage is a substrate bias.

19 . The semiconductor device according to claim 17 ,
wherein the control voltage is a power voltage.

20 . The semiconductor device according to claim 17 ,
wherein each of the first memory cell and the second memory cell includes a transistor for varying a trip point of the memory cell, and the control voltage is a voltage applied to a gate of the transistor.

21 . The semiconductor device according to claim 17 , further comprising,
first and second calculators, wherein the first calculator is configured to calculate an energy function having the first memory cell and the second memory cell as an input, and the second calculator is configured to calculate an energy function having inverted values of the first memory cell and the second memory cell as an input.

22 . The semiconductor device according to claim 17 ,
wherein each of the first memory cell and the second memory cell includes a word line, a first bit line, and a second bit line, the first bit line is able to perform reading and writing when the word line is activated, and the second bit line is constantly able to perform reading.

23 . The semiconductor device according to claim 17 ,
wherein each of the first memory cell and the second memory cell is an SRAM memory cell including a pair of CMOS inverters.

24 . The semiconductor device according to claim 22 ,
wherein each of the first memory cell and the second memory cell is an SRAM memory cell including a pair of CMOS inverters.

25 . A semiconductor device comprising:
a first memory cell; and a second memory cell that interacts with the first memory cell, wherein each of the first memory cell and the second memory cell is an SRAM memory cell including a pair of CMOS inverters, and storage content of the first and second memory cells is stochastically inverted.

26 . The semiconductor device according to claim 25 , further comprising:
a first register that sets temperature and energy; a second register that sets temperature; and a third register that holds current temperature and current energy, wherein applied voltages of the first and second memory cells are changed with passage of time, and when content of the third register reaches a condition designated by the first register, a substrate bias is set to a voltage based on the temperature designated by the second register.

27 . The semiconductor device according to claim 25 , further comprising,
first and second calculators, wherein the first calculator is configured to calculate an energy function having the first memory cell and the second memory cell as an input, and the second calculator is configured to calculate an energy function having inverted values of the first memory cell and the second memory cell as an input.

28 . The semiconductor device according to claim 26 , further comprising,
first and second calculators, wherein the first calculator is configured to calculate an energy function having the first memory cell and the second memory cell as an input, and the second calculator is configured to calculate an energy function having inverted values of the first memory cell and the second memory cell as an input.

29 . The semiconductor device according to claim 25 ,
wherein each of the first memory cell and the second memory cell includes a word line, a first bit line, and a second bit line, the first bit line is able to perform reading and writing when the word line is activated, and the second bit line is constantly able to perform reading.

30 . The semiconductor device according to claim 26 ,
wherein each of the first memory cell and the second memory cell includes a word line, a first bit line, and a second bit line, the first bit line is able to perform reading and writing when the word line is activated, and the second bit line is constantly able to perform reading.

31 . The semiconductor device according to claim 25 ,
wherein substrate biases of the first and second memory cells are controlled, and the storage content is stochastically inverted by dropping threshold voltages of the first and second memory cells.

32 . The semiconductor device according to claim 26 ,
wherein substrate biases of the first and second memory cells are controlled, and the storage content is stochastically inverted by dropping threshold voltages of the first and second memory cells.

Assignees

• Hitachi Ltd

Inventors

• Yoshimura Chihiro
• Yamaoka Masanao
• Sekiguchi Tomonori
• Tomaru Tatsuya

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title