Current pulse generator with integrated bus boost circuit

US10797601B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10797601-B2
Application numberUS-201916515239-A
CountryUS
Kind codeB2
Filing dateJul 18, 2019
Priority dateJul 18, 2018
Publication dateOct 6, 2020
Grant dateOct 6, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

First claim

Opening claim text (preview).

What is claimed is: 1. A current pulse generator integrated circuit, comprising: a boost circuit connected to a boost input terminal and a boost output terminal of the integrated circuit, wherein the boost circuit comprises: a first gate driver circuit having an input for receiving a boost control signal; and a first field effect transistor (FET) having a gate terminal connected to an output of the first gate driver circuit, a drain terminal, and a source terminal connected to ground; a synchronous rectifier connected to the boost input terminal of the integrated circuit and to the drain terminal of the first FET; and a load driver circuit connected to a load driver terminal of the integrated circuit, wherein the load driver circuit comprises: a second gate driver circuit having an input for receiving a load driver control signal; and a second FET having a gate terminal connected to an output of the second gate driver circuit, a drain terminal connected to the load driver terminal of the integrated circuit, and a source terminal connected to ground; wherein the synchronous rectifier comprises a third FET having a gate terminal connected to a boost control voltage, a source terminal connected to the boost input terminal of the integrated circuit, and a drain terminal connected to the boost output terminal of the integrated circuit and to the drain terminal of the first FET, and wherein both the boost circuit and the load driver circuit are monolithically integrated together on a single semiconductor die to form the integrated circuit. 2. The current pulse generator integrated circuit of claim 1 , wherein the first and second FETs are enhancement mode gallium nitride field effect transistors. 3. A pulse generator device, comprising: the current pulse generator integrated circuit of claim 1 ; a voltage source; an inductor connected between the voltage source and the boost input terminal; a capacitor connected to the boost output terminal; and a load connected to the boost output terminal and the load driver terminal of the integrated circuit. 4. A boost converter circuit, comprising: a current pulse generator integrated circuit, comprising; a gate driver circuit having an input for receiving a control signal; a field effect transistor (FET) having a gate terminal connected to an output of the gate driver circuit, a drain terminal connected to a first terminal of the integrated circuit, and a source terminal; and a rectifying element connected to a second terminal of the integrated circuit; wherein the gate driver circuit, the FET, and the rectifying element of the current pulse generator integrated circuit are monolithically integrated on a single semiconductor die; a voltage source; an inductor connected between the voltage source and the first terminal of the current pulse generator circuit; a capacitor having a positive terminal connected to the first terminal of the current pulse generator integrated circuit and a negative terminal connected to the second terminal of the current pulse generator integrated circuit; and a load connected to the capacitor and the second terminal of the current pulse generator integrated circuit. 5. The boost converter circuit of claim 4 , wherein the FET comprises an enhancement mode gallium nitride field effect transistor. 6. The boost converter circuit of claim 4 , wherein the FET of the current pulse generator integrated circuit controls both the charging and the discharging of the capacitor. 7. The boost converter circuit of claim 4 , wherein the capacitor is a floating capacitor. 8. The boost converter circuit of claim 4 , wherein the load is a laser diode.

Assignees

Inventors

Classifications

  • H03K5/02Primary

    by amplifying (H03K5/04 takes precedence) · CPC title

  • H02M3/1584Primary

    with a plurality of power processing stages connected in parallel · CPC title

  • Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

  • switched with a phase shift, i.e. interleaved · CPC title

  • including plural semiconductor devices as final control devices for a single load · CPC title

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What does patent US10797601B2 cover?
A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transist…
Who is the assignee on this patent?
Efficient Power Conversion Corp
What technology area does this patent fall under?
Primary CPC classification H03K5/02. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 06 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).