GaN FET with integrated driver and slew rate control

Patent metadata

Field	Value
Publication number	US-9929652-B1
Application number	US-201615373327-A
Country	US
Kind code	B1
Filing date	Dec 8, 2016
Priority date	Dec 8, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A power circuit is disclosed. The power circuit includes a power capacitor and a power resistor connected to the power capacitor. The power circuit also includes a power integrated circuit, including a GaN-based substrate, a power FET on the substrate, and a driver on the substrate. The driver is configured to charge a gate of the power FET using current from a power node. The power integrated circuit also includes a first power voltage regulator on the substrate, where the driver is configured to receive current from the capacitor through the resistor while the driver charges the gate of the power FET, and where the first power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power FET.

First claim

What is claimed is:

1. A power circuit, comprising:
a power capacitor;
a power resistor, connected to the power capacitor in series; and
a power integrated circuit, comprising:
a GaN-based substrate;
a power FET on the substrate;
a power node connected to the series connected power capacitor and power resistor;
a driver on the substrate, the driver comprising a power supply input connected to the power node, wherein the driver is configured to charge a gate of the power FET using current from the power node; and
a first power voltage regulator on the substrate connected to the power node, wherein the first power voltage regulator is configured to receive a reference voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference voltage is generated at the power node,
wherein the driver is configured to receive current at the substantially fixed voltage via the power supply input from the series connected power capacitor and power resistor and to charge the gate of the power FET with the received current.

2. The power circuit of claim 1 , wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal.

3. The power circuit of claim 2 , wherein the first power voltage regulator is configured to provide current to the capacitor in response to the PWM signal.

4. The power circuit of claim 2 , wherein the driver is configured receive current from the capacitor in response to the PWM signal.

5. The power circuit of claim 1 , wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power FET becoming greater than a threshold.

6. The power circuit of claim 1 , wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold.

7. The power circuit of claim 1 , wherein the power integrated circuit further comprises a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of the driver.

8. A method of using a power circuit, the method comprising:
with a power voltage regulator configured to receive a reference voltage, charging a series connected capacitor and resistor to substantially fixed voltage based on the reference voltage; and
wherein the first power voltage regulator is configured to receive a reference voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference voltage is generated at the power node,
with a driver connected to the series connected capacitor and resistor, receiving at a power input of the driver current from the series connected capacitor and resistor at the substantially fixed voltage, and charging a gate of a power FET with the received current.

9. The method of claim 8 , wherein the power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power FET.

10. The method of claim 8 , wherein the gate of the power FET is charged by the driver while the power voltage regulator does not charge the capacitor.

11. The method of claim 8 , wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the power voltage regulator is configured to provide current to the capacitor in response to the PWM signal.

12. The method of claim 8 , wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the driver is configured receive current from the capacitor in response to the PWM signal.

13. The method of claim 8 , wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power FET becoming greater than a threshold.

14. The method of claim 8 , wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold.

15. A power integrated circuit, comprising:
a GaN-based substrate;
a power FET on the substrate;
a power input/output node;
a driver on the substrate, the driver comprising a power supply input connected to the power input/output node, wherein the driver is configured to charge a gate of the power FET using current from the power input/output node; and
a first power voltage regulator on the substrate connected to the power input/output node, wherein the first power voltage regulator is configured to receive a reference voltage and to cause current to flow out of the power integrated circuit through the power input/output node, such that a voltage based on the reference voltage is generated at the power input/output node,
wherein the driver is configured to receive current flowing into the power integrated circuit at the substantially fixed voltage from the power supply input/output node and to charge the gate of the power FET with the received current.

16. The integrated circuit of claim 15 , wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the first power voltage regulator is configured to provide current to the power input/output node in response to the PWM signal.

17. The integrated circuit of claim 15 , wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the driver is configured to charge the gate of the power FET in response to the PWM signal.

18. The integrated circuit of claim 15 , wherein the first power voltage regulator is configured to provide current to the power input/output node in response to the voltage of the gate of the power FET becoming greater than a threshold.

19. The integrated circuit of claim 15 , wherein the first power voltage regulator comprises a transistor configured to provide the current caused to flow out of the power integrated circuit, wherein the transistor is configured to turn off in response to the voltage of the drain of the power FET becoming less than a threshold.

20. The integrated circuit of claim 15 , further comprising a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of the driver.

Assignees

• Navitas Semiconductor Inc

Inventors

• Ribarich Thomas
• Sharma Santosh
• Zhang Ju
• Giandalia Marco
• Kinzer Daniel Marvin

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H01L29/78

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title