Semiconductor device having air-gap and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016351501-A1
Application number	US-201514874080-A
Country	US
Kind code	A1
Filing date	Oct 2, 2015
Priority date	May 27, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A semiconductor device in which an air-gap located at a side of a bit line stack is extended to an upper part of the bit line stack is disclosed. An embodiment includes: a bit line stack; a plurality of storage node contacts located at both sides of the bit line stack; and an air-gap located between the bit line stack and the storage node contacts, and extended above the bit line stack.

First claim

1 . A semiconductor device comprising:
a bit line stack; a plurality of storage node contacts located at both sides of the bit line stack; and an air-gap located between the bit line stack and the storage node contacts, and extended above the bit line stack, wherein the bit line stack includes: a conductive line; and a hard mask stacked on the conductive line.

2 . (canceled)

3 . The semiconductor device according to claim 1 , wherein the storage node contacts include:
a first storage node contact; and a second storage node contact above the first storage node contact and the bit line stack.

4 . The semiconductor device according to claim 3 , wherein a top surface of the first storage node contact is below a top surface of the bit line stack.

5 . The semiconductor device according to claim 3 , wherein the air-gap is extended above a top surface of the second storage node contact.

6 . The semiconductor device according to claim 3 , wherein the air-gap includes:
a first air-gap located at both sidewalls of the bit line stack; and a second air-gap interposed between the second storage node contacts, which are contiguous, and having a double-layered structure extending from the first air-gap.

7 . The semiconductor device according to claim 6 , wherein the first air-gap has a single-layered structure.

8 . The semiconductor device according to claim 6 , wherein the second air-gap extends from one of the first air-gaps located at both sides of the bit line stack.

9 . The semiconductor device according to claim 6 , wherein the second air-gap has a double-layered structure in which air-gaps are respectively located at facing sidewalls of the second storage node contacts on the basis of the bit line stack interposed therebetween.

10 . The semiconductor device according to claim 6 , wherein the first air-gap is in a spacer insulation film of the bit line stack.

11 . The semiconductor device according to claim 6 , wherein the second air-gap has a U-shaped structure.

12 . A method for fabricating a semiconductor device comprising:
forming a bit line stack; forming a spacer including a first sacrificial film at both sidewalls of the bit line stack; forming a storage node contact damascene pattern defining a storage node contact hole at a position between the bit line stacks; forming a first storage node contact at a lower part of the storage node contact hole; forming a conductive film over the first storage node contact and the bit line stack to bury the storage node contact hole; etching the conductive film to expose the first sacrificial film, and forming a trench; forming a second sacrificial film coupled to the first sacrificial film at an inner sidewall of the trench; forming an interlayer insulation film over the second sacrificial film to bury the trench; etching the conductive film in a direction perpendicular to the bit line stack such that the conductive film is isolated, and forming a second storage node contact; forming an air-gap by etching the first sacrificial film and the second sacrificial film; and forming a capping film such that an upper part of the air-gap is capped with the capping film.

13 . The method according to claim 12 , wherein the forming the spacer includes:
forming a first spacer insulation film over the bit line stack; forming the first sacrificial film over the first spacer insulation film; forming a second spacer insulation film over the first sacrificial film; and etching the first spacer insulation film, the first sacrificial film, and the second spacer insulation film in such a manner that the first spacer insulation film, the first sacrificial film, and the second spacer insulation film are disposed only at a sidewall of the bit line stack.

14 . The method according to claim 12 , wherein the forming the trench includes etching the conductive film in a direction obliquely crossing the bit line stack.

15 . The method according to claim 12 , wherein the forming the second sacrificial film includes:
forming a first insulation film at an inner sidewall of the trench; etching the first insulation film located at a lower part of the trench such that the first sacrificial film is exposed; and forming the second sacrificial film over the first insulation film such that the second sacrificial film is coupled to the first sacrificial film.

Assignees

• Sk Hynix Inc

Inventors

• Chun Jae Houb

Classifications

• H10P50/282

  of inorganic materials · CPC title

• H10P50/264

  by chemical means · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title