DRAM data path sharing via a split local data bus

Patent metadata

Field	Value
Publication number	US-9934827-B2
Application number	US-201514975298-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

First claim

What is claimed is:

1. A memory device, comprising:
a global data bus comprising a first set of lines and a second set of lines;
a local data bus split into a first part and a second part; and
a decoder configurable to transmit a first set of signals via a first set of column select lines to select data for transmission along the first part of the local data bus to the first set of lines of the global data bus, and a second set of signals via a second set of column select lines to select data for transmission along the second part of the local data bus to the second set of lines of the global data bus.

2. The memory device of claim 1 , wherein a width of the local data bus is half of a prefetch width of the memory device.

3. The memory device of claim 2 , wherein the local data bus is configurable to separate logically consecutive data for directing data to the global data bus.

4. The memory device of claim 1 , wherein the memory device comprises at least one of a volatile or a nonvolatile memory device.

5. The memory device of claim 1 , wherein the memory device comprises at least one memory bank.

6. A method, comprising:
receiving signals in a local data bus that is split into a first part and a second part;
directing the signals from the local data bus to a global data bus comprising a first set of lines and a second set of lines; and
transmitting, by a decoder, a first set of signals via a first set of column select lines to select data for transmission along the first part of the local data bus to the first set of lines of the global data bus, and a second set of signals via a second set of column select lines to select data for transmission along the second part of the local data bus to the second set of lines of the global data bus.

7. The method of claim 6 , wherein a width of the local data bus is half of a prefetch width.

8. The method of claim 7 , the method further comprising:
separating logically consecutive data in the local data bus for directing data to the global data bus.

9. The method of claim 6 , wherein the local data bus and the global data bus are included in memory device that comprises at least one of a volatile or a nonvolatile memory device.

10. The method of claim 9 , wherein the volatile or the nonvolatile memory device comprises at least one memory bank.

11. A computational device, comprising:
a processor; and
a memory device coupled to the processor, the memory device comprising:
a global data bus comprising a first set of lines and a second set of lines;
a local data bus split into a first part and a second part and
a decoder configurable to transmit a first set of signals via a first set of column select lines to select data for transmission along the first part of the local data bus to the first set of lines of the global data bus, and a second set of signals via a second set of column select lines to select data for transmission along the second part of the local data bus to the second set of lines of the global data bus.

12. The computational device of claim 11 , wherein a width of the local data bus is half of a prefetch width of the memory device.

13. The computational device of claim 12 , wherein the local data bus is configurable to separate logically consecutive data for directing data to the global data bus.

14. The computational device of claim 11 , wherein local data bus and the global data bus are in a memory device that comprises at least one of a volatile or a nonvolatile memory device.

15. The computational device of claim 11 , wherein the memory device comprises at least one memory bank.

16. The computational device of claim 11 , comprising one or more of:
a display coupled to the memory device;
a network interface communicatively coupled to the processor; or
a battery communicatively coupled to the processor.

17. The memory device of claim 1 , wherein the first set of signals select one half of a word line, and wherein the second set of signals select another half of the word line.

18. The memory device of claim 1 , wherein the first part of the local data bus and the second part of the local data bus are both located in between the first set of lines and the second set of lines of the global data bus.

19. The memory device of claim 1 , wherein a first section and a second section of an array tile are located in between the first set of lines of the global data bus and the second set of lines of the global data bus, and wherein the local data bus is located in between the first section and the second section of the array tile.

20. The method of claim 6 , wherein the first set of signals select one half of a word line, and wherein the second set of signals select another half of the word line.

21. The method of claim 6 , wherein the first part of the local data bus and the second part of the local data bus are both located in between the first set of lines and the second set of lines of the global data bus.

22. The method of claim 6 , wherein a first section and a second section of an array tile are located in between the first set of lines of the global data bus and the second set of lines of the global data bus, and wherein the local data bus is located in between the first section and the second section of the array tile.

23. The computational device of claim 11 , wherein the first set of signals select one half of a word line, and wherein the second set of signals select another half of the word line.

24. The computational device of claim 11 , wherein the first part of the local data bus and the second part of the local data bus are both located in between the first set of lines and the second set of lines of the global data bus.

25. The computational device of claim 11 , wherein a first section and a second section an array tile are located in between the first set of lines of the global data bus and the second set of lines of the global data bus, and wherein the local data bus is located in between the first section and the second section of the array tile.

Assignees

• Intel Corp

Inventors

• Wu Wei
• Tomishima Shigeki
• Lu Shih-Lien L

Classifications

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C2207/107

  Serial-parallel conversion of data or prefetch · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title