Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-10680600-B2
Application number	US-201916377114-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Jul 11, 2005
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

What is claimed is:

1. An RF module comprising: at least one integrated circuit chip;
the at least one integrated circuit chip included in the RF module and further including at least one field effect transistor, the at least one field effect transistor including a gate, a drain, a source, and a body;

wherein, during at least a portion of an off state, the body of the at least one field effect transistor is to be electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

2. The RF module of claim 1 , wherein the at least one field effect transistor comprises a N-type metal oxide semiconductor (NMOS) field effect transistor.

3. The RF module of claim 1 , wherein the at least one field effect transistor is implemented in a silicon on insulator technology.

4. The RF module of claim 1 , wherein the voltage level substantially more negative than the lowest voltage level is more than one volt more negative than the lowest voltage level.

5. The RF module of claim 1 , wherein the body of the at least one field effect transistor is electrically coupled to an accumulated charge sink.

6. The RF module of claim 1 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to improve the linearity of the at least one field effect transistor relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

7. The RF module of claim 1 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to reduce non-linear harmonic and/or intermodulation distortion of RF signals to be propagated by the module, reduction via the at least one field effect transistor being relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

8. The RF module of claim 7 , wherein the power of a third harmonic of the RF signals to be propagated via the RF module is to be lower than −30 dBm at an operating power of +35 dBm power.

9. The RF module of claim 1 , wherein the at least one field effect transistor is included in a stack of field effect transistors included in an RF switch, the RF switch being included in the at least one integrated circuit chip.

10. The RF module of claim 1 , wherein the body of the at least one field effect transistor is electrically coupled to at least two accumulated charge sinks.

11. A communication device comprising: at least one integrated circuit chip;
the at least one integrated circuit chip is included in the communication device and further including an RF switch comprising at least one field effect transistor, the at least one field effect transistor includes a gate, a drain, a source, and a body;
wherein during at least a portion of an off state, the body of the at least one field effect transistor is to be electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

12. The RF module of claim 11 , wherein the at least one field effect transistor comprises a N-type metal oxide semiconductor (NMOS) field effect transistor.

13. The communication device of claim 11 , wherein the at least one field effect transistor is implemented in a silicon on insulator technology.

14. The communication device of claim 11 , wherein the voltage level substantially more negative than the lowest voltage level is more than one volt more negative than the lowest voltage level.

15. The communication device of claim 11 , wherein, the body of the at least one field effect transistor is electrically coupled to an accumulated charge sink.

16. The communication device of claim 11 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to improve the linearity of the at least one field effect transistor relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

17. The communication device of claim 11 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to reduce non-linear harmonic and/or intermodulation distortion of RF signals to be propagated by the communication device, reduction via the at least one field effect transistor being relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

18. The communication device of claim 17 , wherein the power of a third harmonic of the RF signals to be propagated via the RF switch is to be lower than −30 dBm at an operating power of +35 dBm power.

19. The communication device of claim 11 , wherein the at least one field effect transistor is included in a stack of field effect transistors included in an RF switch, the RF switch being included in the at least one integrated circuit chip.

20. The communication device of claim 11 , wherein, during the at least a portion of the off state, the body of the at least one field effect transistor is to be electrically coupled to at least two accumulated charge sinks.

21. An RF front-end comprising: at least one integrated circuit chip and other RF front-end components;
the at least one integrated circuit chip and other RF front-end components included in the RF front-end, the at least one integrated circuit chip further including at least one field effect transistor, the at least one field effect transistor includes a gate, a drain, a source, and a body;
wherein, during at least a portion of the off state, the body of the at least one field effect transistor is to be electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

22. The RF module of claim 21 , wherein the at least one field effect transistor comprises a N-type metal oxide semiconductor (NMOS) field effect transistor.

23. The RF front-end of clai

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Burgener Mark L
• Welstand Robert B

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L29/78681

  Electricity · mapped topic

• H01L29/78684

  Electricity · mapped topic

• H01L29/78615

  Electricity · mapped topic

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title