Replacement metal gate scheme with self-alignment gate for vertical field effect transistors

Patent metadata

Field	Value
Publication number	US-9960254-B1
Application number	US-201715424937-A
Country	US
Kind code	B1
Filing date	Feb 6, 2017
Priority date	Feb 6, 2017
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a fin structure formed over a substrate;
a dummy gate formed over the fin structure, the dummy gate etched by a first amount to expose a top portion of the fin structure;
an first dielectric layer formed adjacent the exposed top portion of the fin structure;
a spacer formed adjacent the first dielectric layer contacting the fin structure, the dummy gate etched further by a second amount after spacer formation;
a second dielectric layer deposited to encapsulate the remaining dummy gate;
an inter-level dielectric (ILD) formed over the second dielectric layer;
at least one hard mask formed over the ILD to access the dummy gate, the dummy gate stripped to form at least one recess; and
a high-k metal gate (HKMG) deposited within the at least one recess.

2. The structure of claim 1 , wherein the dummy gate is laterally etched.

3. The structure of claim 1 , wherein the HKMG directly contacts the fin structure.

4. The structure of claim 1 , further comprising forming a hard mask over the top portion of the fin structure before forming the dummy gate over the fin structure.

5. The structure of claim 4 , wherein, after formation of the HKMG, the dummy gate is etched by a third amount to remove the hard mask formed over the top portion of the fin structure.

6. The structure of claim 5 , wherein the hard mask is etched to expose the top portion of the fin structure.

7. The structure of claim 6 , wherein an epitaxial growth layer is formed directly over the top portion of the fin structure.

8. The structure of claim 7 , wherein, after formation of the epitaxial growth layer, a gate contact, source contact, and a drain contact are formed.

9. The structure of claim 1 , wherein stripping of the dummy gate results in removal of dielectric adjacent the fin structure.

10. The structure of claim 9 , wherein the dummy gate is stripped by wets like hot ammonia.

Assignees

• IBM

Inventors

• Bao Raqiang
• Guo Dechao

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H01L29/401

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic