Delta-sigma loop filters with input feedforward

Patent metadata

Field	Value
Publication number	US-10784891-B2
Application number	US-201816149746-A
Country	US
Kind code	B2
Filing date	Oct 2, 2018
Priority date	May 9, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

First claim

We claim:

1. An analog-to-digital converter (ADC) comprising a delta-sigma loop filter, the delta-sigma loop filter comprising:
a first summing node having a first input coupled to an input of the delta-sigma loop filter;
a first integrator having an input coupled to an output of the first summing node;
a second summing node having a first input coupled to an output of the first integrator;
a second integrator having an input coupled to an output of the second summing node;
a third summing node having a first input coupled to an output of the second integrator;
a third integrator having an input coupled to an output of the third summing node;
a quantizer having an input coupled to an output of the third integrator;
a first input-feedforward path from the input of the delta-sigma loop filter to a second input of the second summing node;
a second input-feedforward path from the input of the delta-sigma loop filter to a second input of the third summing node;
a third input-feedforward path from the input of the delta-sigma loop filter to a third input of the third summing node;
a first feedback path from an output of the quantizer to a second input of the first summing node; and
a second feedback path from the output of the quantizer to a third input of the second summing node.

2. The ADC of claim 1 , the delta-sigma loop filter further comprising a third feedback path from the output of the quantizer to a fourth input of the third summing node.

3. The ADC of claim 2 , wherein the first feedback path, the second feedback path, and the third feedback path are each characterized by a different coefficient.

4. The ADC of claim 1 , further comprising a delay element coupled between the output of the second integrator and the first input of the third summing node.

5. A loop filter comprising:
a first summing node having a first input coupled to an input of the loop filter;
a first integrator having an input coupled to an output of the first summing node;
a second summing node having a first input coupled to an output of the first integrator;
a second integrator having an input coupled to an output of the second summing node;
a third summing node having a first input coupled to an output of the second integrator;
a third integrator having an input coupled to an output of the third summing node;
a quantizer having an input coupled to an output of the third integrator;
a first input-feedforward path from the input of the loop filter to a second input of the third summing node; and
a second input-feedforward path from the input of the loop filter to a third input of the third summing node.

6. The loop filter of claim 5 , further comprising a delay element coupled between the second integrator and the third summing node, the delay element comprising a switched capacitor circuit.

7. The loop filter of claim 5 , further comprising a third input-feedforward path from the input of the loop filter to a second input of the second summing node.

8. The loop filter of claim 5 , further comprising a feedback path coupled between the quantizer and one of the first summing node, the second summing node, and the third summing node and including a digital-to-analog converter (DAC) configured to determine at least one of a feedback gain and loop zeros and poles for the feedback path.

9. A device, comprising:
a digital module; and
an analog module having an output coupled to an input of the digital module, the analog module comprising an analog-to-digital converter (ADC) comprising a delta-sigma loop filter, the delta-sigma loop filter comprising:
a first summing node having a first input coupled to an input of the delta-sigma loop filter;
a first integrator having an input coupled to an output of the first summing node;
a second summing node having a first input coupled to an output of the first integrator;
a second integrator having an input coupled to an output of the second summing node;
a third summing node having a first input coupled to an output of the second integrator;
a third integrator having an input coupled to an output of the third summing node;
a quantizer having an input coupled to an output of the third integrator;
a first input-feedforward path from the input of the delta-sigma loop filter to a second input of the second summing node;
a second input-feedforward path from the input of the delta-sigma loop filter to a second input of the third summing node;
a third input-feedforward path from the input of the delta-sigma loop filter to a third input of the third summing node;
a first feedback path from an output of the quantizer to a second input of the first summing node; and
a second feedback path from the output of the quantizer to a third input of the second summing node.

10. The device of claim 9 , further comprising:
a modem coupled to an output of the digital module; and
a microcontroller coupled to an output of the modem.

11. The device of claim 10 , further comprising a radio including the digital module, the analog module, and the modem.

12. The device of claim 10 , further comprising a system-on-chip (SOC) including the digital module, the analog module, the modem, and the microcontroller.

Assignees

• Microchip Tech Inc

Inventors

• Rajaee Omid
• Bagheri Rahim
• Pourbagheri Saeed
• Mehrjoo Mohammad
• Bagheri Mahdi
• Chiem Edwin
• Wang Jun

Classifications

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03H17/0225

  Measures concerning the multipliers · CPC title

• H03M3/398

  among different converter types · CPC title

• H03H17/0411

  using DELTA modulation · CPC title

• H03H2017/0295

  Changing between two filter characteristics · CPC title