Suppressing signal transfer function peaking in a feedforward delta sigma converter

Patent metadata

Field	Value
Publication number	US-9564916-B2
Application number	US-201615067847-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Jun 3, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A modified topology for a CTDSM (referred herein as “SCFF”) can effectively deal with signal transfer function (STF) peaking, an inherent property of continuous time feedforward delta sigma converters. The SCFF approach involves providing an additional digital-to-analog (DAC) feedback path to the input of the second integrator (incurring an additional DAC in the circuitry, converting the output of the quantizer into an analog signal and feeding the analog signal to the input of the second integrator). Furthermore, the SCFF approach involves providing two feed-ins: a first feed-in to the input of the second integrator and a second feed-in to the input of the third integrator. The first feed-in can be negative. Advantageously, the modified continuous time delta sigma modulator implementing this approach alleviates some of the peaking issues in the signal transfer function while still enjoy low power consumption.

First claim

What is claimed is:

1. A modified feedforward delta sigma analog-to-digital converter, comprising:
a cascade of integrators receiving an analog input of the converter;
a quantizer for quantizing a sum of the outputs of the integrators and generating a digital output of the converter, and providing feedback to input of a first one of the integrators;
a feedback path from the digital output of the quantizer to an input of a second one of the integrators; and
one or more feed-in paths from the analog input of the converter to inputs of one or more ones of the integrators subsequent to the first one of the integrators, the one or more feed-in paths comprising a first feed-in path from the analog input of the converter to the input of the second one of the integrators and a second feed-in path from the analog input of the converter to the input of a third one of the integrators.

2. The converter of claim 1 , wherein the cascade of integrators comprises one or more continuous time integrators.

3. The converter of claim 1 , wherein the first feed-in path has negative gain.

4. The converter of claim 1 , wherein the second feed-in path has positive gain.

5. The converter of claim 1 , wherein the one or more feed-in paths to inputs of one or more ones of the integrators subsequent to the first one of the integrators are implemented with resistors and/or capacitors.

6. The converter of claim 1 , wherein the feedback path from the digital output of the quantizer to the input of the second one of the integrators comprises one or more of the following: switched current circuits, switched capacitor circuits, and switched resistor circuits.

7. The converter of claim 1 , wherein inputs of one or more ones of the integrators subsequent to a second one of the integrators do not receive the analog input of the converter.

8. The converter of claim 1 , further comprising:
a main feedback path from the output of the quantizer to the input of the first integrator.

9. The converter of claim 1 , wherein one or more integrators subsequent to the first one and second one of the integrators do not receive feedback from the output of the quantizer.

10. The converter of claim 1 , wherein the cascade of integrators is a part of a loop filter, and the loop filter is an elliptical loop filter.

11. A continuous time feedforward delta sigma analog-to-digital converter comprising:
a cascade of integrators receiving an analog input of the converter; and
a quantizer for quantizing a sum of the outputs of the integrators and generating a digital output of the converter, and providing feedback to input of a first one of the integrators;
wherein the cascade of integrators form an elliptical loop filter.

12. The converter of claim 11 , further comprising:
a main feedback path from the output of the quantizer to the input of a first one of the integrators; and
a further feedback path from the digital output of the quantizer to an input of a second one of the integrators.

13. The converter of claim 11 , further comprising:
one or more feed-in paths from the analog input of the converter to inputs of one or more ones of the integrators subsequent to the first one of the integrators.

14. A method for delta sigma modulation, comprising:
filtering an analog input signal by a loop filter, wherein filtering the analog input signal comprises receiving a feedback signal at inputs of a first integrator and a second integrator of the loop filter, and receiving the analog input signal at inputs of the second integrator and a third integrator of the loop filter;
quantizing, a summed signal having all outputs of integrators of the loop filter.

15. The method of claim 14 , wherein providing the feedback signal and the analog input signal to the second one of the N integrators prevents the loop filter from switching from operating as an Nth order loop filter to operating a first order loop filter when filtering the analog input at higher frequencies.

16. A method for delta sigma modulation, comprising:
filtering an analog input signal by an elliptical loop filter, wherein filtering the analog input signal comprises receiving a feedback signal at inputs of a first integrator and a second integrator of the elliptical loop filter, and receiving the analog input signal at one or more inputs of one or more integrators of the elliptical loop filter;
quantizing a summed signal having all outputs of integrators of the elliptical loop filter.

17. The method of claim 16 , further comprising:
suppressing, by the elliptical loop filter, adjacent channels for the feedforward delta sigma analog-to-digital converter.

18. The converter of claim 10 , wherein one or more feed-in paths comprises a negative gain feed-in path from the analog input of the converter to the input of a second one of the integrators.

19. The converter of claim 10 , wherein the one or more feed-in paths to inputs of one or more ones of the integrators subsequent to the first one of the integrators are implemented with resistors and/or capacitors.

20. The converter of claim 10 , wherein the feedback path from the digital output of the quantizer to the input of the second one of the integrators comprises one or more of the following: switched current circuits, switched capacitor circuits, and switched resistor circuits.

Assignees

• Analog Devices Inc

Inventors

• Bandyopadhyay Abhishek

Classifications

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M3/422 Primary

  having one quantiser only · CPC title

• H03M3/45

  with distributed feedforward inputs, i.e. with forward paths from the modulator input to more than one filter stage · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title