Receiver with signal arrival detection capability

Patent metadata

Field	Value
Publication number	US-9720875-B2
Application number	US-201313949837-A
Country	US
Kind code	B2
Filing date	Jul 24, 2013
Priority date	Jul 24, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A receiver includes a phase click detector, a controller, and a comparator. The phase click detector detects phase clicks in an input signal, where a phase click corresponds to a change in phase of at least a first threshold. The controller is coupled to the phase click detector for calculating a number of phase clicks within one or more time periods. The comparator compares the number of phase clicks within the one or more time periods, and provides an arrival signal if the number of phase clicks is less than a second threshold.

First claim

What is claimed is:

1. A receiver comprising:
a circuit for representing an input signal as a sequence of complex numbers each having a respective amplitude and a respective phase;
a phase click detector for detecting phase clicks in said input signal, wherein a phase click corresponds to a change in said phase of at least a first threshold from a first one of said complex numbers to a second one of said complex numbers;
a controller coupled to the phase click detector for calculating a number of phase clicks within one or more time periods; and
a comparator for comparing said number of phase clicks within said one or more time periods, and providing an arrival signal if said number of phase clicks is less than a second threshold.

2. The receiver of claim 1 wherein said comparator further provides a first pass arrival signal if said number of phase clicks is less than a third threshold, wherein said third threshold is less than said second threshold.

3. The receiver of claim 1 wherein said phase click detector comprises a phase click counter for counting said phase clicks in said input signal within said time period.

4. The receiver of claim 1 , wherein said controller comprises:
a window timer having an output for providing a window time signal periodically; and
a valid counter having an increment input, a clock input for receiving said window time signal, and an output for providing a value equal to said number of phase clicks within said one or more time periods.

5. The receiver of claim 1 , further comprising:
a deviation detector for providing a deviation match signal in response to a difference between a low detected deviation of a phase change signal and a high detected deviation of said phase change signal being in a predetermined time period,
wherein said controller is further responsive to said deviation match signal for calculating said number of phase clicks within said one or more time periods.

6. The receiver of claim 4 , wherein said controller further comprises:
a state machine, coupled to said phase click detector, for controlling said value of said valid counter in response to said number of phase clicks within said one or more time periods.

7. The receiver of claim 4 , wherein said controller further comprises:
a state machine, coupled to said phase click detector, for controlling said value of said valid counter in response to said number of phase clicks within said one or more time periods, and said value of said valid counter.

8. The receiver of claim 4 , wherein said controller further comprises:
a state machine, coupled to said phase click detector, for subtracting a number from said value of said valid counter in response to said number of phase clicks within said one or more time periods, and said value of said valid counter being greater than a predetermined number.

9. The receiver of claim 4 , wherein said controller further comprises:
a state machine, coupled to said phase click detector, for resetting said valid counter in response to said number of phase clicks within said one or more time periods, and said value of said valid counter being less than a predetermined number.

10. A receiver comprising:
an analog receiver having an input for receiving a radio frequency (RF) signal, and an output for providing a digital intermediate frequency signal as a sequence of complex numbers each having a respective amplitude and a respective phase; and
a digital processor having an input for receiving said digital intermediate frequency signal, and an output for providing a demodulated signal, comprising:
a signal arrival detector having an output for providing at least one of an arrival signal and a first pass arrival signal, wherein said signal arrival detector provides said arrival signal in response to a number of phase clicks being less than a first threshold within one or more time periods, and wherein said signal arrival detector provides said first pass arrival signal in response to said number of phase clicks being less than a second threshold within one or more time periods, wherein a phase click corresponds to a change in said phase of at least a third threshold from a first one of said complex numbers to a second one of said complex numbers; and
a demodulator responsive to said arrival signal, for demodulating said digital intermediate frequency signal.

11. The receiver of claim 10 , wherein said demodulator initiates automatic frequency compensation (AFC) on a preamble in response to said arrival signal.

12. The receiver of claim 10 , wherein said receiver enters a sleep mode in response to said signal arrival detector not asserting at least one of said arrival signal and said first pass arrival signal within said one or more time periods.

13. The receiver of claim 10 , wherein said demodulator initiates bit clock recovery (BCR) on a preamble in response to said arrival signal.

14. The receiver of claim 10 , wherein said receiver modifies a receive frequency in response to at least one of said arrival signal and said first pass arrival signal.

15. The receiver of claim 10 , wherein said RF signal comprises a Meter-Bus (M-Bus) compatible short preamble.

16. The receiver of claim 10 , wherein said signal arrival detector comprises:
a window timer having an output for providing a window time signal periodically in response to a number of bit times of a preamble.

17. A method comprising:
receiving an input signal;
converting said input signal to an intermediate frequency signal comprising a sequence of complex numbers each having a respective amplitude and a respective phase;
determining a number of phase clicks in said intermediate frequency signal in one or more time periods, wherein a phase click corresponds to a change in said phase of at least a first threshold from a first one of said complex numbers to a second one of said complex numbers; and
comparing said number of phase clicks within said one or more time periods to a second threshold, and providing at least one of an arrival signal if said number of phase clicks is less than said second threshold, and a first pass arrival signal if said number of phase clicks is less than a third threshold.

18. The method of claim 17 wherein said determining said number of phase clicks further comprises:
controlling a value of said number of phase clicks within said one or more time periods in response to said number of phase clicks in said intermediate frequency signal in said one or more time periods.

19. The method of claim 18 wherein said determining said number of phase clicks further comprises:
freezing said value of said number of phase clicks within said one or more time periods in response to a deviation match signal.

Assignees

• Silicon Lab Inc

Inventors

• De Ruijter Hendricus
• Li Wentao

Classifications

• H04L27/22

  Demodulator circuits; Receiver circuits · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title

• H04J3/1605

  Fixed allocated frame structures · CPC title

• H04W56/00

  Synchronisation arrangements · CPC title