Method for producing ceramic multi-layer components

Patent metadata

Field	Value
Publication number	US-10784435-B2
Application number	US-201515500965-A
Country	US
Kind code	B2
Filing date	Jul 21, 2015
Priority date	Aug 26, 2014
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

Methods for producing ceramic multi-layer components and multi-layer components made by such methods. A method includes the following steps: providing green layers for the ceramic multi-layer components, stacking the green layers into a stack and subsequently pressing the stack into a block, singulating the block into partial blocks each having a longitudinal direction, thermally treating the partial blocks and subsequently machining surfaces of the partial blocks. Recesses are produced on the surfaces of the partial blocks during the machining, and the partial blocks are singulated.

First claim

The invention claimed is:

1. A method for producing ceramic multi-layer components, comprising:
providing green layers for the ceramic multi-layer components,
stacking the green layers into a stack and subsequently pressing the stack into a block,
singulating the block into partial blocks each having a longitudinal direction,
thermally treating the partial blocks and subsequent to the thermally treating, machining surfaces of the partial blocks, wherein recesses are produced on the surfaces of the partial blocks during the machining,
singulating the partial blocks subsequent to the thermally treating.

2. The method according to claim 1 ,
wherein the partial blocks are singulated along the recesses.

3. The method according to claim 2 , wherein the recesses produced during the machining of the surfaces of the partial blocks extend in a direction transverse to the longitudinal direction.

4. The method according to claim 3 , wherein the recesses are produced in the surfaces of the partial blocks by grinding during the machining of the surfaces of the partial blocks.

5. The method according to claim 4 ,
wherein, during the machining of the partial blocks, the surfaces of the partial blocks are abraded in a planar manner, and during the machining of the surfaces of the partial blocks, the recesses are produced in the surfaces of the partial blocks by grinding.

6. The method according to claim 2 , wherein the recesses are produced in the surfaces of the partial blocks by grinding during the machining of the surfaces of the partial blocks.

7. The method according to claim 1 ,
wherein the recesses produced during the machining of the surfaces of the partial blocks extend in a direction transverse to the longitudinal direction.

8. The method according to claim 1 ,
wherein the recesses are produced in the surfaces of the partial blocks by grinding during the machining of the surfaces of the partial blocks.

9. The method according to claim 8 , wherein the recesses are V-shaped.

10. The method according to claim 1 ,
wherein, during the machining of the partial blocks, the surfaces of the partial blocks are abraded in a planar manner, and during the machining of the surfaces of the partial blocks, the recesses are produced in the surfaces of the partial blocks by grinding.

11. The method according to claim 1 ,
wherein, after the thermally treating, the green layers form, in each of the partial blocks, ceramic layers arranged one on top of another and first and second electrically conductive layers arranged between the ceramic layers,
after the machining of the surfaces of the partial blocks, selective etching the partial blocks, and
wherein material is removed from the first electrically conductive layers on a first side face of the partial block and in those of the recesses that are produced in the first side face during the selective etching, and
wherein material is removed from the second electrically conductive layers on a second side face of the partial block and in those of the recesses that are produced in the second side face during the selective etching.

12. The method according to claim 1 ,
wherein the recesses are V-shaped.

Assignees

• Epcos Ag
• Tdk Electronics Ag

Inventors

• Ottlinger Marion
• Windisch Peter
• Krumphals Robert
• Reinisch Manfred
• Galler Martin
• Kügerl Georg

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• Y10T29/42

  Piezoelectric device making · CPC title

• H01G4/304

  obtained from a another capacitor · CPC title

• H01L41/337

  Electricity · mapped topic

• H01L41/273

  Electricity · mapped topic