Multiple column per channel CCD sensor architecture for inspection and metrology

Patent metadata

Field	Value
Publication number	US-10778925-B2
Application number	US-201916439297-A
Country	US
Kind code	B2
Filing date	Jun 12, 2019
Priority date	Apr 6, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.

First claim

The invention claimed is:

1. A multiple-column-per-channel charge-coupled-device (CCD) image sensor comprising:
a pixel array including a plurality of pixels arranged in a plurality of columns and a plurality of pixel rows, the pixel array being configured to generate image charges and to sequentially transfer each said image charge between associated pixels disposed in a corresponding said column in response to a plurality of pixel control signals, whereby a set of image charges disposed in a first said pixel row is simultaneously transferred to an adjacent second said pixel row during each cycle of said plurality of pixel control signals;
a readout circuit comprising:
a plurality of buffer cells disposed to simultaneously receive image charges from an edge pixel row in response to one or more buffer control signals such that each buffer cell receives a corresponding image charge from an associated pixel of said edge pixel row upon assertion of said one or more buffer control signals;
a plurality of transfer gates disposed in said plurality of columns and arranged in a plurality of transfer gate rows including a first transfer gate row disposed to receive a corresponding image charge from an associated said buffer cell, each of said plurality of transfer gates being operably controlled by and associated transfer clock signal;
a summing gate coupled to a last transfer gate row; and
an output circuit coupled to the summing gate,
wherein said plurality of transfer gates are configured and coupled such that asserting a first transfer clock signal during a first time periodcauses a first image charge to be transferred from a first said buffer cell to a first transfer gate, and causes a second image charge to be transferred from a second said transfer gate to a third said transfer gate,
wherein said first buffer cell and said first transfer gate are disposed in a first said column, and said second transfer gate and said third transfer gate are disposed in a second said column, and
wherein the summing gate is configured to receive the second image charge from the second column during a second time period subsequent to the first time period in accordance with a summing gate control signal, and the summing gate is further configured to receive the first image charge from the first column during a third time period subsequent to the second time period in accordance with the summing gate control signal and
wherein a clock rate of the summing gate control signal is at least two times faster than a line clock rate of the plurality of pixel control signals.

2. The sensor of claim 1 ,
wherein said plurality of transfer gates are further configured such that asserting said first transfer clock signal during said first time periodfurther causes a third image charge to be transferred from a fourth said transfer gate to a fifth said transfer gate,
wherein said fourth transfer gate and said fifth transfer gate are disposed in a third said column, and
wherein said first transfer gate and said fourth transfer gate are disposed in said first transfer gate row, said second transfer gate and said fifth transfer gate are disposed in a second transfer gate row disposed below the first transfer gate row, and said third transfer gate is disposed in a third transfer gate row disposed below the second transfer gate row.

3. The sensor of claim 1 , wherein the output circuit comprises a floating diffusion configured to receive and store said image charges, and an amplifier coupled to the floating diffusion and configured to generate a corresponding output voltage signal in accordance with each said image charge stored on the floating diffusion.

4. The sensor of claim 1 , wherein the readout circuit includes a plurality of readout structures, each said readout structure connected to an associated group of said columns and includes a corresponding plurality of said transfer gates, a corresponding said summing gate, and a corresponding said output circuit.

5. The sensor of claim 4 , wherein said amplifier of each said readout structure comprises a metal interconnect, wherein capacitances of the metal interconnects of different amplifiers are substantially similar.

6. The sensor of claim 4 , wherein each said amplifier comprises a metal interconnect, wherein areas of the metal interconnects of different amplifiers are substantially similar.

7. The sensor of claim 4 , wherein the array of pixels consists of one or more rows of pixels.

8. The sensor of claim 2 , wherein the sensor further comprises an output control circuit configured to operably control the summing gate such that a fourth image charge is transferred from a sixth said transfer gate to said summing gate during the first time period, wherein said sixth transfer gate is disposed in said first column and disposed in said third transfer gate row.

9. The sensor of claim 8 , wherein said plurality of transfer gates are further configured such that asserting a second transfer clock signal during a second time periodcauses a fourth image charge to be transferred from a second said buffer cell to a seventh said transfer gate, causes said first image charge to be transferred from said first transfer gate to an eighth said transfer gate, and causes said third image charge to be transferred from said fifth said transfer gate to a ninth said transfer gate,
wherein the said second buffer cell is disposed in said third column,
wherein said seventh transfer gate is disposed in said second column and said first transfer gate row,
wherein said eighth transfer gate is disposed in said first column and said second transfer gate row, and
wherein said ninth transfer gate is disposed in said third column and said third transfer gate row.

10. The sensor of claim 9 , wherein the output control circuit is further configured to operably control the output circuit and the summing gate such that said fourth image charge is transferred from said summing gate to a floating diffusion and said second image charge is transferred from said third transfer gate to said summing gate during the second time period.

11. The sensor of claim 10 , wherein said plurality of transfer gates are further configured such that asserting a third transfer clock signal during a third time periodcauses a sixth image charge to be transferred from a third said buffer cell to said fourth transfer gate, causes said first image charge to be transferred from said eighth transfer gate to said sixth transfer gate, and causes said fourth image charge to be transferred from said seventh transfer gate to said second transfer gate.

12. The sensor of claim 11 , wherein the output control circuit is further configured to operably control the output circuit and the summing gate such that said second image charge is transferred from said summing gate to said floating diffusion and said third image charge is transferred from said ninth transfer gate to said summing gate during the third time period.

13. The sensor of claim 12 , further comprising a buffer control circuit configured to control the first, second and third buffer cells to simultaneously respectively receive seventh, eighth and ninth image charges from said edge pixel row during the third time period and after the sixth image charge is transferred from said third said buffer cell to said fourth transfer gate.

14. A method of inspecting a sample, the method comprising:
directing and focusing radiation onto the sample while moving the sample relative to a source of said radiation;
directing received radiation from the sample to an image sensor, the image sensor comprising a multiple-column-per-channel charge-c

Assignees

• Kla Tencor Corp

Inventors

• Chuang Yung-Ho Alex
• Zhang Jingjing
• Zamek Sharon
• Fielden John
• Contarato Devis
• Brown David L

Classifications

• G01N21/956 Primary

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