Semiconductor memory device and detection clock pattern generating method thereof

Patent metadata

Field	Value
Publication number	US-10777246-B2
Application number	US-202016778431-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Sep 21, 2012
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

First claim

What is claimed is:

1. A graphic memory system operating in synchronization with a clock signal, the graphic memory system comprising:
a dynamic random access memory (DRAM) device configured to output read data read from memory cells of the DRAM device in response to a read command, the DRAM device including a mode register storing a mode register set signal and an error detecting code (EDC) pattern generator outputting cyclic redundancy check data during a first time period and error detection code patterns during a second time period through error detection code pins, the cyclic redundancy check data being generated based on the read data, and the error detection code patterns being generated based on the mode register set signal, wherein the read data is output after column address strobe (CAS) latency from the read command, and the cyclic redundancy check data is output before and after the read data, and there is no gap between the cyclic redundancy check data and the error detection code patterns; and
a graphic processor unit (GPU) device coupled to the DRAM device, the GPU device configured to receive the read data and the cyclic redundancy check data during the first time period, and to receive the error detection code patterns during the second time period and perform a clock-data recovery (CDR) function based on the error detection code patterns and the clock signal,
wherein the error detection code patterns are a hold pattern when the mode register set signal is a first level, and the error detection code patterns are a random pattern when the mode register set signal is a second level respectively, and the second level is different from the first level.

2. The graphic memory system of claim 1 , wherein the error detection code patterns include a first error detection code pattern outputted through a first error detection code pin and a second error detection code pattern outputted through a second error detection code pin, the first error detection code pattern and the second error detection code pattern are identical in phase from each other.

3. The graphic memory system of claim 1 , wherein the error detection code patterns include a first error detection code pattern outputted through a first error detection code pin and a second error detection code pattern outputted through a second error detection code pin, the first error detection code pattern and the second error detection code pattern are inverted in phase from each other.

4. The graphic memory system of claim 3 , wherein the first error detection code pattern and the second error detection code pattern combined together form a differential signal pattern.

5. The graphic memory system of claim 1 , wherein the hold pattern is a toggling pattern having a same frequency rate with the read data.

6. The graphic memory system of claim 1 , wherein the random pattern is a pseudo random pattern generated by a pseudo random pattern generator which includes linear feedback shift registers.

7. The graphic memory system of claim 6 , wherein the random pattern reduces electro-magnetic interference (EMI) during transmission of the read data to the GPU device.

8. The graphic memory system of claim 1 , wherein the GPU device is further configured to set the mode register set signal during a mode register set period.

9. The graphic memory system of claim 1 , wherein the GPU device adjusts a phase difference between the clock signal and the error detection code patterns during the CDR function.

10. A graphic memory system operating in synchronization with a clock signal, the graphic memory system comprising:
a dynamic random access memory (DRAM) device configured to output read data read from memory cells of the DRAM device in response to a read command, the DRAM device including an error detecting code (EDC) pattern generator outputting cyclic redundancy check data during a first time period and error detection code patterns during a second time period through error detection code pins, the cyclic redundancy check data being generated based on the read data, and the error detection code patterns being random patterns; and
a graphic processor unit (GPU) device coupled to the DRAM device, the GPU device configured to receive the read data and the cyclic redundancy check data during the first time period, and to receive the error detection code patterns during the second time period and perform a clock-data recovery (CDR) function based on the error detection code patterns and the clock signal, and
wherein the error detection code patterns are random patterns, and
wherein the GPU device adjusts a phase difference between the clock signal and the error detection code patterns during the CDR function.

11. The graphic memory system of claim 10 , wherein the error detection code patterns include a first error detection code pattern outputted through a first error detection code pin and a second error detection code pattern outputted through a second error detection code pin, the first error detection code pattern and the second error detection code pattern are identical in phase from each other.

12. The graphic memory system of claim 10 , wherein the error detection code patterns include a first error detection code pattern outputted through a first error detection code pin and a second error detection code pattern outputted through a second error detection code pin, the first error detection code pattern and the second error detection code pattern are inverted in phase from each other.

13. The graphic memory system of claim 12 , wherein the first error detection code pattern and the second error detection code pattern combined together form a differential signal pattern.

14. The graphic memory system of claim 10 , wherein each random pattern is a pseudo random pattern generated by a pseudo random pattern generator which includes linear feedback shift registers.

15. The graphic memory system of claim 10 , wherein each random pattern reduces electro-magnetic interference (EMI) during transmission of the read data to the GPU device.

16. The graphic memory system of claim 10 , wherein the GPU device is further configured to set a mode register set signal for replacing the random patterns with a hold pattern.

17. A graphic memory system of claim 10 , operating in synchronization with a clock signal, the graphic memory system comprising:
a dynamic random access memory (DRAM) device configured to output read data read from memory cells of the DRAM device in response to a read command, the DRAM device including an error detecting code (EDC) pattern generator outputting cyclic redundancy check data during a first time period and error detection code patterns during a second time period through error detection code pins, the cyclic redundancy check data being generated based on the read data, and the error detection code patterns being random patterns; and
a graphic processor unit (GPU) device coupled to the DRAM device, the GPU device configured to receive the read data and the cyclic redundancy check data during the first time period, and to receive the error detection code patterns during the second time period and perform a clock-data recovery (CDR) function based on the error detection code patterns and the clock signal,
wherein the error detection code patterns are random patterns, and
wherein the read data is output after column address strobe (CAS) latency from the read command.

18. The graphic memory system of claim 17 , wherein the cyclic redundancy check data is output later than the read data.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Doo Su Yeon
• Bae Seungjun
• Kim Sihong
• Song Hosung

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title